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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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EMC2104 Fiches technique(PDF) 73 Page - SMSC Corporation |
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EMC2104 Fiches technique(HTML) 73 Page - SMSC Corporation |
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73 / 101 page  Dual RPM-Based PWM Fan Controller with Hardware Thermal Shutdown Datasheet SMSC EMC2104 73 Revision 1.74 (05-08-08) DATASHEET 6.29 Fan Drive Fail Band Registers The Fan Drive Fail Band Registers store the number of tach counts used by the Fan Drive Fail detection circuitry. This circuitry is activated when the fan drive setting high byte is at FFh. When it is enabled, the actual measured fan speed is compared against the target fan speed. These registers are only used when the FSC is active. This circuitry is used to indicate that the target fan speed at full drive is higher than the fan is actually capable of reaching. If the measured fan speed does not exceed the target fan speed minus the Fan Drive Fail Band Register settings for a period of time longer than set by the DRIVE_FAIL_CNTx[1:0] bits then the DRIVE_FAIL status bit will be set and an interrupt generated. 6.30 TACH Target Registers The TACH Target Registers hold the target tachometer value that is maintained each of the RPM based Fan Speed Control Algorithms. The value in the TACH Target Registers will always reflect the current TACH Target value. If the Look Up Table is active and configured to operate in RPM Mode, then this register will be read only. Writing to this register will have no affect and the data will not be stored. Table 6.44 Fan Drive Fail Band Registers ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 4Ah R/W Fan 1 Drive Fail Band Low Byte 16 8 4 2 1 - - - 00h 4Bh R/W Fan 1 Drive Fail Band High Byte 4096 2048 1024 512 256 128 64 32 00h 8Ah R/W Fan 2 Drive Fail Band Low Byte 16 8 4 2 1 - - - 00h 8Bh R/W Fan 2 Drive Fall Band High Byte 4096 2048 1024 512 256 128 64 32 00h Table 6.45 TACH Target Registers ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 4Ch R/W TACH Target 1 Low Byte 16 84 21 - - - F8h 4Dh R/W TACH Target 1 High Byte 4096 2048 1024 512 256 128 64 32 FFh 8Ch R TACH Target 2 Low Byte 16 84 21 - - - F8h 8Dh R/W TACH Target 2 High Byte 4096 2048 1024 512 256 128 64 32 FFh |
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