PIC16F18345 datasheet(97/442 Pages) MICROCHIP

97 / 442 page

 2015 Microchip Technology Inc.

Preliminary

DS40001799A-page 97

PIC16(L)F18313/18323

PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4

U-0

R/W/HS-0/0

U-0

R/W/HS-0/0 R/W/HS-0/0

—CWG1IF

—

CCP2IF

CCP1IF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

HS = Hardware set

bit 7

Unimplemented:

Read as ‘0’

bit 6

CWG1IF:

CWG1 Interrupt Flag bit

= CWG1 has gone into shutdown

= CWG1 is operating normally, or interrupt cleared

bit 5-2

Unimplemented:

Read as ‘0’

bit 1

CCP2IF:

CCP2 Interrupt Flag bit

bit 0

CCP1IF:

CCP1 Interrupt Flag bit

Value

CCPM Mode

Capture

Compare

PWM

Capture occurred

(must be cleared in software)

Compare match occurred

(must be cleared in software)

Output trailing edge occurred

(must be cleared in software)

Capture did not occur

Compare match did not occur

Output trailing edge did not occur

Value

CCPM Mode

Capture

Compare

PWM

Capture occurred

(must be cleared in software)

Compare match occurred

(must be cleared in software)

Output trailing edge occurred

(must be cleared in software)

Capture did not occur

Compare match did not occur

Output trailing edge did not occur

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User

software

should

ensure

the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

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