PIC16F18345 datasheet(95/442 Pages) MICROCHIP

95 / 442 page

 2015 Microchip Technology Inc.

Preliminary

DS40001799A-page 95

PIC16(L)F18313/18323

PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

U-0

R/W/HS-0/0

R/W/HS-0/0 R/W/HS-0/0

U-0

R/W/HS-0/0

—C2IF(1)

C1IF

NVMIF

—

NCO1IF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

HS = Hardware set

bit 7

Unimplemented

: Read as ‘0’

bit 6

C2IF:

Comparator C2 Interrupt Flag bit(1)

= Comparator 2 interrupt asserted

= Comparator 2 interrupt not asserted

bit 5

C1IF:

Comparator C1 Interrupt Flag bit

= Comparator 1 interrupt asserted

= Comparator 1 interrupt not asserted

bit 4

NVMIF

: NVM Interrupt Flag bit

= The NVM has completed a programming task

= NVM interrupt not asserted

bit 3-1

Unimplemented

: Read as ‘0’

bit 0

NCO1IF:

Direct Digital Synthesizer Interrupt Flag bit

= The NCO has rolled over

= No NCO interrupt is asserted

Note 1:

Comparator C2 not available on PIC16(L)F18313 devices.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User

software

should

ensure

the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

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