PIC16F18345 datasheet(73/442 Pages) MICROCHIP

73 / 442 page

 2015 Microchip Technology Inc.

Preliminary

DS40001799A-page 73

PIC16(L)F18313/18323

6.4

Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) allows the device

to continue operating should the external oscillator fail.

The FSCM is enabled by setting the FCMEN bit in the

Configuration Words. The FSCM is applicable to all

external Oscillator modes (LP, XT, HS, EC and

Secondary Oscillator).

FIGURE 6-9:

FSCM BLOCK DIAGRAM

6.4.1

FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by

comparing the external oscillator to the FSCM sample

clock. The sample clock is generated by dividing the

LFINTOSC by 64. See Figure 6-9. Inside the fail

detector block is a latch. The external clock sets the

latch on each falling edge of the external clock. The

sample clock clears the latch on each rising edge of the

sample clock. A failure is detected when an entire

half-cycle of the sample clock elapses before the

external clock goes low.

6.4.2

FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the

device clock to the HFINTOSC at 1 MHz clock

frequency and sets the bit flag OSFIF of the PIR3

OSFIE bit of the PIE3 register is also set. The device

firmware can then take steps to mitigate the problems

that may arise from a failed clock. The system clock will

continue to be sourced from the internal clock source

until the device firmware successfully restarts the

external oscillator and switches back to external

operation, by writing to the NOSC and NDIV bits of the

OSCCON1 register.

6.4.3

FAIL-SAFE CONDITION CLEARING

The Fail-Safe condition is cleared after a Reset,

executing a SLEEP instruction or changing the NOSC

and NDIV bits of the OSCCON1 register. When

switching to the external oscillator or PLL, the OST is

restarted. While the OST is running, the device

continues to operate from the INTOSC selected in

OSCCON1. When the OST times out, the Fail-Safe

condition is cleared after successfully switching to the

external clock source. The OSFIF bit should be cleared

prior to switching to the external clock source. If the

Fail-Safe condition still exists, the OSFIF flag will again

become set by hardware.

External

LFINTOSC

÷ 64

31 kHz

(~32

s)

488 Hz

(~2 ms)

Clock Monitor

Latch

Clock

Failure

Detected

Oscillator

Clock

Sample Clock

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