PIC16F18345 datasheet(42/442 Pages) MICROCHIP

42 / 442 page

PIC16(L)F18313/18323

DS40001799A-page 42

Preliminary

 2015 Microchip Technology Inc.

3.3

PCL and PCLATH

The Program Counter (PC) is 15 bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC<14:8>) is not directly

readable or writable and comes from PCLATH. On any

Reset, the PC is cleared. Figure 3-3 shows the five

situations for the loading of the PC.

FIGURE 3-3:

LOADING OF PC IN

DIFFERENT SITUATIONS

3.3.1

MODIFYING PCL

Executing any instruction with the PCL register as the

destination simultaneously causes the Program

Counter PC<14:8> bits (PCH) to be replaced by the

contents of the PCLATH register. This allows the entire

contents of the program counter to be changed by writ-

ing the desired upper seven bits to the PCLATH regis-

ter. When the lower eight bits are written to the PCL

to the values contained in the PCLATH register and

those being written to the PCL register.

3.3.2

COMPUTED GOTO

A computed GOTO is accomplished by adding an offset to

the program counter (ADDWF PCL). When performing a

table read using a computed GOTO method, care should

be exercised if the table location crosses a PCL memory

boundary (each 256-byte block). Refer to Application

Note AN556, “Implementing a Table Read” (DS00556).

3.3.3

COMPUTED FUNCTION CALLS

A computed function CALL allows programs to maintain

tables of functions and provide another way to execute

state machines or look-up tables. When performing a

table read using a computed function CALL, care

should be exercised if the table location crosses a PCL

memory boundary (each 256-byte block).

If using the CALL instruction, the PCH<2:0> and PCL

registers are loaded with the operand of the CALL

instruction.

The CALLW instruction enables computed calls by

combining PCLATH and W to form the destination

address. A computed CALLW is accomplished by

loading the W register with the desired address and

executing CALLW. The PCL register is loaded with the

value of W and PCH is loaded with PCLATH.

3.3.4

BRANCHING

The branching instructions add an offset to the PC.

This allows relocatable code and code that crosses

page boundaries. There are two forms of branching,

BRW

and BRA. The PC will have incremented to fetch

the next instruction in both cases. When using either

branching instruction, a PCL memory boundary may be

crossed.

If using BRW, load the W register with the desired

unsigned address and execute BRW. The entire PC will

be loaded with the address PC + 1 + W.

If using BRA, the entire PC will be loaded with PC + 1,

the signed value of the operand of the BRA instruction.

PCL

PCH

PCL

PCH

ALU Result

PCLATH

Instruction with

PCL as

Destination

GOTO, CALL

OPCODE <10:0>

PCLATH

PCL

PCH

PCLATH

CALLW

PCL

PCH

PC + W

BRW

PCL

PCH

PC + OPCODE <8:0>

BRA

PIC16F18345 Fiches technique(PDF) 42 Page - Microchip Technology

PIC16F18345 Fiches technique(HTML) 42 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Fiches technique Télécharger

Lien URL