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PIC16F18345 Fiches technique(PDF) 31 Page - Microchip Technology |
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PIC16F18345 Fiches technique(HTML) 31 Page - Microchip Technology |
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31 / 442 page ![]() Bank 8 CPU CORE REGISTERS; see Table 3-2 for specifics 40Ch-41Fh — — Unimplemented — — Bank 9 48Ch-497h — — Unimplemented — — 498h NCO1ACCL NCO1ACC<7:0> 0000 0000 0000 0000 499h NCO1ACCH NCO1ACC<15:8> 0000 0000 0000 0000 49Ah NCO1ACCU ― ― ― ― NCO1ACC<19:16> ---- 0000 ---- 0000 49Bh NCO1INCL NCO1INC<7:0> 0000 0001 0000 0001 49Ch NCO1INCH NCO1INC<15:8> 0000 0000 0000 0000 49Dh NCO1INCU ― ― ― ― NCO1INC<19:16> ---- 0000 ---- 0000 49Eh NCO1CON N1EN ― N1OUT N1POL ― ― ― N1PFM 0-00 ---0 0-00 ---0 49Fh NCO1CLK N1PWS<2:0> ― ― ― N1CKS<1:0> 000- --00 000- --00 TABLE 3-4: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note 1: Only on PIC16F18313/18323. |
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