PIC16F18345 datasheet(70/442 Pages) MICROCHIP

70 / 442 page

PIC16(L)F18313/18323

DS40001799A-page 70

Preliminary

 2015 Microchip Technology Inc.

6.2.2.3

Internal Oscillator Frequency

Adjustment

The internal oscillator is factory-calibrated. This

internal oscillator can be adjusted in software by writing

to the OSCTUNE register (Register 6-3).

The default value of the OSCTUNE register is 00h. The

value is a 6-bit two’s complement number. A value of

3Fh will provide an adjustment to the maximum

frequency. A value of 0h will provide an adjustment to

the minimum frequency.

When the OSCTUNE register is modified, the oscillator

frequency will begin shifting to the new frequency. Code

execution continues during this shift. There is no

indication that the shift has occurred.

OSCTUNE does not affect the LFINTOSC frequency.

Operation of features that depend on the LFINTOSC

clock source frequency, such as the Power-up Timer

(PWRT), Watchdog Timer (WDT), Fail-Safe Clock

Monitor (FSCM) and peripherals, are not affected by the

change in frequency.

6.2.2.4

LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is

a factory calibrated 31 kHz internal clock source.

The LFINTOSC is the clock source for the Power-up

Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe

Clock Monitor (FSCM).

The LFINTOSC is selected as the clock source through

one of the following methods:

• Programming the RSTOSC<2:0> bits of

Configuration Word 1 to enable LFINTOSC.

• Write to the NOSC<2:0> bits of the OSCCON1

6.2.2.5

Oscillator Status and Manual Enable

The ‘ready’ status of each oscillator is displayed in the

OSCSTAT1 register (Register 6-4). The oscillators can

also be manually enabled through the OSCEN register

(Register 6-6). Manual enables make it possible to

verify the operation of the EXTOSC or SOSC crystal

oscillators. This can be achieved by enabling the

selected oscillator, then watching the corresponding

‘ready’ state of the oscillator in the OSCSTAT1 register.

6.3

Clock Switching

The system clock source can be switched between

external and internal clock sources via software using

the New Oscillator Source (NOSC) and New Divider

selection request (NDIV) bits of the OSCCON1 register.

The following clock sources can be selected using the

following:

• External Oscillator (EXTOSC)

• High-Frequency Internal Oscillator (HFINTOSC)

• Low-Frequency Internal Oscillator (LFINTOSC)

• Secondary Oscillator (SOSC)

• EXTOSC with 4x PLL

• HFINTOSC with 2x PLL

6.3.1

NEW OSCILLATOR SOURCE

(NOSC) AND NEW DIVIDER

SELECTION REQUEST (NDIV) BITS

The New Oscillator Source (NOSC) and New Divider

selection request (NDIV) bits of the OSCCON1 register

select the system clock source that is used for the CPU

and peripherals.

When new values of NOSC and NDIV are written to

OSCCON1, the current oscillator selection will

continue to operate while waiting for the new clock

source to indicate that it is stable and ready. In some

cases, the newly requested source may already be in

use, and is ready immediately. In the case of a

divider-only change, the new and old sources are the

same, so the old source will be ready immediately. The

device may enter Sleep while waiting for the switch as

described in Section 6.3.3, Clock Switch and Sleep.

When the new oscillator is ready, the New Oscillator is

Ready (NOSCR) bit of OSCCON3 and the Clock

Switch Interrupt Flag (CSWIF) bit of PIR3 become set

(CSWIF = 1). If Clock Switch Interrupts are enabled

(CLKSIE = 1), an interrupt will be generated at that

time. The Oscillator Ready (ORDY) bit of OSCCON3

can also be polled to determine when the oscillator is

ready in lieu of an interrupt.

If the Clock Switch Hold (CSWHOLD) bit of OSCCON3

is clear, the oscillator switch will occur when the New

Oscillator is Ready bit (NOSCR) is set, and the

interrupt (if enabled) will be serviced at the new

oscillator setting.

If CSWHOLD is set, the oscillator switch is suspended,

while execution continues using the current (old) clock

source. When the NOSCR bit is set, software should:

• Set CSWHOLD = 0 so the switch can complete,

• Copy COSC into NOSC to abandon the switch.

If DOZE is in effect, the switch occurs on the next clock

cycle, whether or not the CPU is operating during that

cycle.

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