PIC16F18345 datasheet(93/442 Pages) MICROCHIP

93 / 442 page

 2015 Microchip Technology Inc.

Preliminary

DS40001799A-page 93

PIC16(L)F18313/18323

PIR0: PERIPHERAL INTERRUPT STATUS REGISTER 0

U-0

R/W/HS-0/0

R-0

U-0

R/W/HS-0/0

—

—TMR0IF

IOCIF

—

INTF(1)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

HS= Hardware Set

bit 7-6

Unimplemented:

Read as ‘0’

bit 5

TMR0IF:

TMR0 Overflow Interrupt Flag bit

= TMR0 register has overflowed (must be cleared in software)

= TMR0 register did not overflow

bit 4

IOCIF:

Interrupt-on-Change Interrupt Flag bit (read-only)

= An enabled edge was detected by the IOC module. One of the IOCF bits is set.

= No enabled edge is was detected by the IOC module. None of the IOCF bits is set.

Pins are individually masked via IOCxP and IOCxN.

bit 3-1

Unimplemented:

Read as ‘0’

bit 0

INTF:

INT External Interrupt Flag bit(1)

= The INT external interrupt occurred (must be cleared in software)

= The INT external interrupt did not occur

Note 1:

The External Interrupt GPIO pin is selected by INTPPS (Register 12-1).

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User

software

should

ensure

the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

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