PIC16F18345 datasheet(45/442 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

Preliminary

DS40001799A-page 45

PIC16(L)F18313/18323

FIGURE 3-7:

ACCESSING THE STACK EXAMPLE 4

3.4.2

OVERFLOW/UNDERFLOW RESET

If the STVREN bit in Configuration Words is

programmed to ‘1’, the device will be Reset if the stack

is PUSHed beyond the sixteenth level or POPed

beyond the first level, setting the appropriate bits

(STKOVF or STKUNF, respectively) in the PCON

3.5

Indirect Addressing

The INDF registers are not physical registers. Any

instruction that accesses an INDF register actually

accesses the register at the address specified by the

File Select Registers (FSR). If the FSR address

specifies one of the two INDF registers, the read will

return ‘0’ and the write will not occur (though Status bits

may be affected). The FSR register value is created by

the pair FSRnH and FSRnL.

The FSR registers form a 16-bit address that allows an

addressing space with 65536 locations. These locations

are divided into four memory regions:

• Traditional Data Memory

• Linear Data Memory

• Program Flash Memory

• EEPROM

3.5.1

TRADITIONAL DATA MEMORY

The traditional data memory is a region from FSR

address 0x000 to FSR address 0xFFF. The addresses

correspond to the absolute addresses of all SFR, GPR

and common registers.

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

Return Address

0x00

STKPTR = 0x10

When the stack is full, the next CALL or

an interrupt will set the Stack Pointer to

0x10. This is identical to address 0x00

so the stack will wrap and overwrite the

return address at 0x00. If the Stack

Overflow/Underflow Reset is enabled, a

Reset will occur and location 0x00 will

not be overwritten.

Return Address

TOSH:TOSL

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