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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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PIC16F18345 Fiches technique(PDF) 6 Page - Microchip Technology |
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PIC16F18345 Fiches technique(HTML) 6 Page - Microchip Technology |
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6 / 442 page  TABLE 2: 14/16-PIN ALLOCATION TABLE (PIC16(L)F18323) RA0 13 12 ANA0 — C1IN0+ — DAC1OUT — — — — — — — — — IOC Y ICDDAT/ ICSPDAT RA1 12 11 ANA1 VREF+C1IN0- C2IN0- — DAC1REF+ —— — — — — — — — IOC Y ICDCLK/ ICSPCLK RA2 11 10 ANA2 VREF- — — DAC1REF- — T0CKI(1) — — CWG1IN(1) — — — — INT(1) IOC Y — RA3 4 3 —— — — — — — — — — — — — — IOC Y MCLR VPP RA4 3 2 ANA4 — — — — — T1G(1) SOSCO — — — — — — — IOC Y CLKOUT OSC2 RA5 2 1 ANA5 —— — — — T1CKI(1) SOSCIN SOSCI —— — — — CLCIN3(1) — IOC Y CLKIN OSC1 RC0 10 9 ANC0 — C2IN0+ — — — — — — — SCK(1) SCL(1,3,4) — — — IOC Y — RC1 9 8 ANC1 — C1IN1- C2IN1- —— — — — — — SDI(1) SDA(1,3,4) — CLCIN2(1) — IOC Y — RC2 8 7 ANC2 — C1IN2- C2IN2- — — MDCIN1(1) — — — — — — — — IOC Y — RC3 7 6 ANC3 — C1IN3- C2IN3- —— MDMIN(1) — CCP2(1) —— SS(1) — CLCIN0(1) — IOC Y — RC4 6 5 ANC4 — — — — — — — — — — — CLCIN1(1) — IOC Y — RC5 5 4 ANC5 —— — — MDCIN2(1) — CCP1(1) —— — RX(1) DT(1,3) —— IOC Y — VDD 1 16 — — — — — — — — — — — — — — — — VDD VSS 14 13 —— — — — — — — — — — — — — — — VSS OUT(2) — — — — C1OUT NCO — DSM TMR0 CCP1 PWM5 CWG1A SDA(3) CK CLC1OUT CLKR — — — ——— — C2OUT —— — — CCP2 PWM6 CWG1B SCL(3) DT(3) CLC2OUT —— — — — — — — — — — — — — — CWG1C SDO TX — — — — ——— — — — — — — — — CWG1D SCK —— — — — — Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-1. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3. 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. 4: These pins are configured for I2C™ logic levels as described in Section 12.3 “Bidirectional Pins”; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register. |
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