PIC16F18345 datasheet(51/442 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

Preliminary

DS40001799A-page 51

PIC16(L)F18313/18323

CONFIG2: CONFIGURATION WORD 2: SUPERVISORS

R/P-1

U-1

R/P-1

U-1

DEBUG

STVREN

PPS1WAY

—BORV

—

bit 13

bit 8

R/P-1

U-1

R/P-1

BOREN1

BOREN0

LPBOREN

—

WDTE1

WDTE0

PWRTE

MCLRE

bit 7

bit 0

Legend:

R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as ‘1’

‘0’ = Bit is cleared

‘1’ = Bit is set

n = Value when blank or after Bulk Erase

bit 13

DEBUG:

Debugger Enable bit(2)

1 = OFF

Background debugger disabled; ICSPCLK and ICSPDAT are general purpose I/O pins

0 = ON

Background debugger enabled; ICSPCLK and ICSPDAT are dedicated to the debugger

bit 12

STVREN:

Stack Overflow/Underflow Reset Enable bit

1 = ON

Stack Overflow or Underflow will cause a Reset

0 = OFF

Stack Overflow or Underflow will not cause a Reset

bit 11

PPS1WAY:

PPSLOCKED One-Way Set Enable bit

1 = ON

The PPSLOCKED bit can be cleared and set only once; PPS registers remain locked after one clear/set

cycle

0 = OFF

The PPSLOCKED bit can be set and cleared repeatedly (subject to the unlock sequence)

bit 10

Unimplemented:

Read as ‘1’

bit 9

BORV:

Brown-out Reset Voltage Selection bit(1)

1 = LOW

Brown-out Reset voltage (VBOR) set to 1.9V on LF, and 2.45V on F devices

0 = HIGH

Brown-out Reset voltage (VBOR) set to 2.7V

The higher voltage setting is recommended for operation at or above 16 MHz.

bit 8

Unimplemented:

Read as ‘1’

bit 7-6

BOREN<1:0>:

Brown-out Reset Enable bits

When enabled, Brown-out Reset Voltage (VBOR) is set by the BORV bit

11 = ON

Brown-out Reset is enabled; SBOREN bit is ignored

10 = SLEEP

Brown-out Reset is enabled while running, disabled in Sleep; SBOREN bit is ignored

01 = SBOREN

Brown-out Reset is enabled according to SBOREN

00 = OFF

Brown-out Reset is disabled

bit 5

LPBOREN:

Low-Power BOR Enable bit

1 = OFF

ULPBOR is disabled

0 = ON

ULPBOR is enabled

bit 4

Unimplemented:

Read as ‘1’

bit 3-2

WDTE<1:0>:

Watchdog Timer Enable bit

11 = ON

WDT is enabled; SWDTEN is ignored

10 = SLEEP

WDT is enabled while running and disabled in Sleep/Idle; SWDTEN is ignored

01 = SWDTEN

WDT is controlled by the SWDTEN bit in the WDTCON register

00 = OFF

WDT is disabled; SWDTEN is ignored

bit 1

PWRTE:

Power-up Timer Enable bit

1 = OFF

PWRT is disabled

0 = ON

PWRT is enabled

bit 0

MCLRE:

Master Clear (MCLR) Enable bit

If LVP = 1:

RA3 pin function is MCLR.

If LVP = 0:

1 = ON

MCLR pin is MCLR.

0 = OFF

MCLR pin function is port-defined function.

Note

See VBOR parameter for specific trip point voltages.

The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and

programmers. For normal device operation, this bit should be maintained as a ‘1’.

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