PIC16F18345 datasheet(96/442 Pages) MICROCHIP

96 / 442 page

PIC16(L)F18313/18323

DS40001799A-page 96

Preliminary

 2015 Microchip Technology Inc.

PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3

R/W/HS-0/0

U-0

R/W/HS-0/0 R/W/HS-0/0

OSFIF

CSWIF

—

CLC2IF

CLC1IF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

HS = Hardware set

bit 7

OSFIF:

Oscillator Failsafe Interrupt Flag bit

= Oscillator fail-safe interrupt has occurred

= No oscillator fail-safe interrupt

bit 6

CSWIF:

Clock Switch Complete Interrupt Flag bit

= The clock switch module indicates an interrupt condition

= The clock switch module does not indicate an interrupt condition

bit 5-2

Unimplemented:

Read as ‘0’

bit 1

CLC2IF:

CLC2 Interrupt Flag bit

= The CLC2OUT interrupt condition has been met

= No CLC2 interrupt

bit 0

CLC1IF:

Direct Digital Synthesizer Interrupt Flag bit

= The CLC1OUT interrupt condition has been met

= No CLC1 interrupt

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User

software

should

ensure

the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

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