PIC16F18345 datasheet(94/442 Pages) MICROCHIP

94 / 442 page

PIC16(L)F18313/18323

DS40001799A-page 94

Preliminary

 2015 Microchip Technology Inc.

PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W/HS-0/0

R/W-0/0

R/W/HS-0/0

R/W/HS-0/0 R/W/HS-0/0

TMR1GIF

ADIF

RCIF

TXIF

SSP1IF

BCL1IF

TMR2IF

TMR1IF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

HS = Hardware set

bit 7

TMR1GIF

: Timer1 Gate Interrupt Flag bit

= The Timer1 Gate has gone inactive (the gate is closed)

= The Timer1 Gate has not gone inactive

bit 6

ADIF:

Analog-to-Digital Converter (ADC) Interrupt Flag bit

= The A/D conversion completed

= The A/D conversion is not completed

bit 5

RCIF:

EUSART Receive Interrupt Flag bit

= The EUSART receive buffer is not empty

= The EUSART receive buffer is empty

bit 4

TXIF

: EUSART Transmit Interrupt Flag bit

= The EUSART receive buffer is not empty

= The EUSART receive buffer is empty

bit 3

SSP1IF

: Synchronous Serial Port (MSSP) Interrupt Flag bit

= The Transmission/Reception/Bus Condition is complete (must be cleared in software)

= Waiting for the Transmission/Reception/Bus Condition in progress

bit 2

BCL1IF:

MSSP Bus Collision Interrupt Flag bit

= A bus collision was detected (must be cleared in software)

= No bus collision was detected

bit 1

TMR2IF:

Timer2 to PR2 Interrupt Flag bit

= TMR2 to PR2 match occurred (must be cleared in software)

= No TMR2 to PR2 match occurred

bit 0

TMR1IF:

Timer1 Overflow Interrupt Flag bit

= TMR1 overflow occurred (must be cleared in software)

= No TMR1 overflow occurred

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User

software

should

ensure

the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

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