PIC16F18345 datasheet(69/442 Pages) MICROCHIP

69 / 442 page

 2015 Microchip Technology Inc.

Preliminary

DS40001799A-page 69

PIC16(L)F18313/18323

6.2.2

INTERNAL CLOCK SOURCES

The device may be configured to use the internal

oscillator block as the system clock by performing one

of the following actions:

• Program the RSTOSC<2:0> bits in Configuration

Words to select the INTOSC clock source, which

will be used as the default system clock upon a

device Reset.

• Write the NOSC<2:0> bits in the OSCCON1

internal oscillator during run-time. See

Section 6.3 “Clock Switching”

for more

information.

The function of the OSC2/CLKOUT pin is determined

by the CLKOUTEN bit in Configuration Words.

The internal oscillator block has two independent

oscillators that can produce two internal system clock

sources.

The

HFINTOSC

(High-Frequency

Internal

Oscillator) is factory-calibrated and operates up

to 32 MHz. The frequency of HFINTOSC can be

selected through the OSCFRQ Frequency

Selection register, and fine-tuning can be done

via the OSCTUNE register.

The

LFINTOSC

(Low-Frequency

Internal

Oscillator) is factory-calibrated and operates at

31 kHz.

6.2.2.1

HFINTOSC

The High-Frequency Internal Oscillator (HFINTOSC) is

a precision digitally-controlled internal clock source

that produces a stable clock up to 32 MHz. The

HFINTOSC can be enabled through one of the

following methods:

• Programming the RSTOSC<2:0> bits in

Configuration Word 1 to ‘110’ (1 MHz) or ‘000’

(32 MHz) to set the oscillator upon device

Power-up or Reset.

• Write to the NOSC<2:0> bits of the OSCCON1

The HFINTOSC frequency can be selected by setting

the HFFRQ<2:0> bits of the OSCFRQ register.

The NDIV<3:0> bits of the OSCCON1 register allow for

the division of the output of the selected clock source

by a range between 1:1 and 1:512.

6.2.2.2

2x PLL

The oscillator module contains a PLL that can be used

with the HFINTOSC clock source to provide a system

clock source. The input frequency to the PLL is limited

to 8, 12, or 16 MHz, which will yield a system clock

source of 16, 24, or 32 MHz, respectively. The PLL

may be enabled for use by one of two methods:

Program the RSTOSC bits in the Configuration

Word 1 to '000' to enable the HFINTOSC (32

MHz). This setting configures the HFFRQ<2:0>

bits to '110' (16 MHz) and activates the 2x PLL.

Write '000' the NOSC<2:0> bits in the

OSCCON1 register to enable the 2x PLL, and

write the correct value into the HFFRQ<2:0> bits

of the OSCFRQ register to select the desired

system clock frequency. See Register 6-6 for

more information.

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