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PIC16F18345 Fiches technique(PDF) 90 Page - Microchip Technology |
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PIC16F18345 Fiches technique(HTML) 90 Page - Microchip Technology |
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90 / 442 page ![]() PIC16(L)F18313/18323 DS40001799A-page 90 Preliminary 2015 Microchip Technology Inc. REGISTER 7-4: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 —C2IE(1) C1IE NVMIE — — — NCO1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 C2IE: Comparator C2 Interrupt Enable bit(1) 1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt bit 5 C1IE: Comparator C1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt bit 4 NVMIE: NVM Interrupt Enable Bit 1 = ENVM task complete interrupt enabled 0 = NVM interrupt not enabled bit 3-1 Unimplemented: Read as ‘0’ bit 0 NCO1IE: NCO Interrupt Enable bit 1 = NCO rollover interrupt enabled 0 = NCO rollover interrupt not enabled Note 1: Comparator C2 not available on PIC16(L)F18313 devices. Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. |
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