SH7205 datasheet(22/1904 Pages) RENESAS

22 / 1904 page

Rev. 1.00 Mar. 25, 2008 Page xxii of xxxii

18.3.2 I

2C Bus Control Register 2 (ICCR2)..................................................................... 848

18.3.3 I

2C Bus Mode Register (ICMR)............................................................................ 850

18.3.4 I

2C Bus Interrupt Enable Register (ICIER)........................................................... 852

18.3.5 I

2C Bus Status Register (ICSR)............................................................................. 854

18.3.6 Slave Address Register (SAR).............................................................................. 857

18.3.7 I

2C Bus Transmit Data Register (ICDRT) ............................................................ 857

18.3.8 I

2C Bus Receive Data Register (ICDRR).............................................................. 858

18.3.9 I

2C Bus Shift Register (ICDRS)............................................................................ 858

18.3.10 NF2CYC Register (NF2CYC).............................................................................. 859

18.4

Operation ........................................................................................................................... 860

18.4.1 I

2C Bus Format...................................................................................................... 860

18.4.2 Master Transmit Operation ................................................................................... 861

18.4.3 Master Receive Operation .................................................................................... 863

18.4.4 Slave Transmit Operation ..................................................................................... 865

18.4.5 Slave Receive Operation....................................................................................... 868

18.4.6 Clocked Synchronous Serial Format .................................................................... 869

18.4.7 Noise Filter ........................................................................................................... 873

18.4.8 Example of Use..................................................................................................... 874

18.5

Interrupt Requests ..............................................................................................................878

18.6

Bit Synchronous Circuit..................................................................................................... 879

18.7

Usage Notes ....................................................................................................................... 881

18.7.1 Note on Setting for Multi-Master Operation......................................................... 881

18.7.2 Note on Master Receive Mode ............................................................................. 881

18.7.3 Note on Setting ACKBT in Master Receive Mode............................................... 881

18.7.4 Note on the States of Bits MST and TRN when Arbitration is Lost..................... 882

Section 19 Serial Sound Interface with FIFO (SSIF)........................................ 883

19.1

Features.............................................................................................................................. 883

19.2

Input/Output Pins...............................................................................................................886

19.3

Register Description .......................................................................................................... 887

19.3.1 Control Register (SSICR) ..................................................................................... 889

19.3.2 Status Register (SSISR) ........................................................................................ 895

19.3.3 Transmit Data Register (SSITDR)........................................................................ 899

19.3.4 Receive Data Register (SSIRDR) ......................................................................... 899

19.3.5 FIFO Control Register (SSIFCR) ......................................................................... 900

19.3.6 FIFO Status Register (SSIFSR) ............................................................................ 903

19.3.7 FIFO Data Register (SSIFDR).............................................................................. 906

19.4

Operation Description........................................................................................................ 907

19.4.1 Bus Format ........................................................................................................... 907

19.4.2 Non-Compressed Modes....................................................................................... 908

SH7205 Fiches technique(PDF) 22 Page - Renesas Technology Corp

SH7205 Fiches technique(HTML) 22 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Fiches technique Télécharger

Lien URL