SH7205 datasheet(92/1904 Pages) RENESAS

No de pièce	SH7205

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

PDF	1904 Pages

Scroll/Zoom	100%

Fabricant	RENESAS [Renesas Technology Corp]

Site Internet	http://www.renesas.com

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92 / 1904 page

Section 2 CPU

Rev. 1.00 Mar. 25, 2008 Page 60 of 1868

REJ09B0372-0100

Addressing

Mode

Instruction

Format

Effective Address Calculation

Equation

The 20-bit immediate data (imm) for the MOVI20

instruction is sign-extended.

Sign-

extended

imm (20 bits)

—

Immediate

#imm:20

The 20-bit immediate data (imm) for the MOVI20S

instruction is shifted by eight bits to the left, the

upper bits are sign-extended, and the lower bits are

padded with zero.

Sign-extended

imm (20 bits) 00000000

31 27

—

#imm:8

The 8-bit immediate data (imm) for the TST, AND,

OR, and XOR instructions is zero-extended.

—

#imm:8

The 8-bit immediate data (imm) for the MOV, ADD,

and CMP/EQ instructions is sign-extended.

—

#imm:8

The 8-bit immediate data (imm) for the TRAPA

instruction is zero-extended and then quadrupled.

—

#imm:3

The 3-bit immediate data (imm) for the BAND, BOR,

BXOR, BST, BLD, BSET, and BCLR instructions

indicates the target bit location.

—

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