SH7205 datasheet(73/1904 Pages) RENESAS

73 / 1904 page

Section 1 Overview

Rev. 1.00 Mar. 25, 2008 Page 41 of 1868

REJ09B0372-0100

Classification

Symbol

I/O

Name

Function

IDED15 to

IDED0

I/O

Data bus

Bidirectional data bus

IDEA2 to IDEA0 O

Address bus

IODACK#

DMA

acknowledge

Primary channel DMA acknowledge

IODREQ

DMA request

Primary channel DMA request

IDECS#1,

IDECS#0

Chip select

Primary channel chip select

IDEIOWR#

Write

Primary channel disk write

IDEIORD#

Read

Primary channel disk read

IDEIORDY

Ready

Primary channel ready signal

IDEINT

Interrupt request

Primary channel interrupt request

IDERST#

Reset

Primary channel ATAPI device reset

AT attachment

packet interface

(ATAPI)

DIRECTION

Direction

External level shifter direction signal

R, G, B

RGB output

RGB analog output pins

REXT

External

reference input

External reference input pin for D/A

converter

CBU

External

capacitance

output

External capacitance output pin for

D/A converter

VIHSYNC

HSYNC signal

HSYNC signal input

VIVSYNC

VSYNC signal

VSYNC signal input

VICLK

Pixel clock

Pixel clock input

VIDATA7 to

VIDATA0

Image data

Image data input

VICLKENB

Clock enable

Indicates that pixel data is valid

CSYNC

CSYNC signal

Composite sync signal after graphic

processing

2D engine (2DG)

DCLKIN

Dot clock

Dot clock input

SH7205 Fiches technique(PDF) 73 Page - Renesas Technology Corp

SH7205 Fiches technique(HTML) 73 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Fiches technique Télécharger

Lien URL