SH7205 datasheet(90/1904 Pages) RENESAS

No de pièce	SH7205

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

PDF	1904 Pages

Scroll/Zoom	100%

Fabricant	RENESAS [Renesas Technology Corp]

Site Internet	http://www.renesas.com

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90 / 1904 page

Section 2 CPU

Rev. 1.00 Mar. 25, 2008 Page 58 of 1868

REJ09B0372-0100

Addressing

Mode

Instruction

Format

Effective Address Calculation

Equation

Indexed GBR

indirect

@(R0, GBR)

The effective address is the sum of GBR value

and R0.

GBR

GBR + R0

TBR duplicate

indirect with

displacement

(disp:8,

TBR)

The effective address is the sum of TBR value

and an 8-bit displacement (disp). The value of

disp is zero-extended, and is multiplied by 4.

TBR

+ disp

× 4

(TBR

+ disp

× 4)

disp

(zero-extended)

Contents of

address (TBR

+ disp

× 4)

PC indirect with

displacement

@(disp:8,

PC)

The effective address is the sum of PC value and

an 8-bit displacement (disp). The value of disp is

zero-extended, and is doubled for a word

operation, and quadrupled for a longword

operation. For a longword operation, the lowest

two bits of the PC value are masked.

H'FFFFFFFC

PC + disp

× 2

PC & H'FFFFFFFC

+ disp

× 4

2/4

(for longword)

disp

(zero-extended)

Word:

PC + disp

× 2

Longword:

PC &

H'FFFFFFFC +

disp

× 4

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