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SH7205 Fiches technique(PDF) 93 Page - Renesas Technology Corp

No de pièce SH7205
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
PDF  1904 Pages
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Fabricant  RENESAS [Renesas Technology Corp]
Site Internet  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7205 Fiches technique(HTML) 93 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 1.00 Mar. 25, 2008 Page 61 of 1868
REJ09B0372-0100
2.3.3
Instruction Format
The instruction formats and the meaning of source and destination operands are described below.
The meaning of the operand depends on the instruction code. The symbols used are as follows:
• xxxx: Instruction code
• mmmm: Source register
• nnnn: Destination register
• iiii: Immediate data
• dddd: Displacement
Table 2.9
Instruction Formats
Instruction Formats
Source
Operand
Destination
Operand
Example
0 format
xxxx
xxxx
xxxx
xxxx
15
0
—
—
NOP
—
nnnn: Register
direct
MOVT
Rn
Control register or
system register
nnnn: Register
direct
STS
MACH,Rn
R0 (Register direct) nnnn: Register
direct
DIVU
R0,Rn
Control register or
system register
nnnn: Register
indirect with pre-
decrement
STC.L SR,@-Rn
mmmm: Register
direct
R15 (Register
indirect with pre-
decrement)
MOVMU.L
Rm,@-R15
R15 (Register
indirect with post-
increment)
nnnn: Register
direct
MOVMU.L
@R15+,Rn
n format
xxxx
xxxx
xxxx
nnnn
15
0
R0 (Register direct) nnnn: (Register
indirect with post-
increment)
MOV.L R0,@Rn+



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