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SH7205 Fiches technique(PDF) 94 Page - Renesas Technology Corp

No de pièce SH7205
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
PDF  1904 Pages
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Fabricant  RENESAS [Renesas Technology Corp]
Site Internet  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7205 Fiches technique(HTML) 94 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 1.00 Mar. 25, 2008 Page 62 of 1868
REJ09B0372-0100
Instruction Formats
Source
Operand
Destination
Operand
Example
mmmm: Register
direct
Control register or
system register
LDC
Rm,SR
mmmm: Register
indirect with post-
increment
Control register or
system register
LDC.L @Rm+,SR
mmmm: Register
indirect
—
JMP
@Rm
mmmm: Register
indirect with pre-
decrement
R0 (Register direct) MOV.L @-Rm,R0
m format
xxxx
mmmm
xxxx
xxxx
15
0
mmmm: PC relative
using Rm
—
BRAF
Rm
mmmm: Register
direct
nnnn: Register
direct
ADD
Rm,Rn
mmmm: Register
direct
nnnn: Register
indirect
MOV.L Rm,@Rn
mmmm: Register
indirect with post-
increment (multiply-
and-accumulate)
nnnn*: Register
indirect with post-
increment (multiply-
and-accumulate)
MACH, MACL
MAC.W
@Rm+,@Rn+
mmmm: Register
indirect with post-
increment
nnnn: Register
direct
MOV.L
@Rm+,Rn
mmmm: Register
direct
nnnn: Register
indirect with pre-
decrement
MOV.L
Rm,@-Rn
nm format
nnnn
xxxx
xxxx
15
0
mmmm
mmmm: Register
direct
nnnn: Indexed
register indirect
MOV.L
Rm,@(R0,Rn)
md format
xxxx
dddd
15
0
mmmm
xxxx
mmmmdddd:
Register indirect
with displacement
R0 (Register direct) MOV.B
@(disp,Rm),R0



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