SH7205 datasheet(10/1904 Pages) RENESAS

10 / 1904 page

Rev. 1.00 Mar. 25, 2008 Page x of xxxii

Section 3 Floating-Point Unit (FPU)................................................................... 91

3.1

Features................................................................................................................................ 91

3.2

Data Formats........................................................................................................................ 92

3.2.1

Floating-Point Format............................................................................................. 92

3.2.2

Non-Numbers (NaN) .............................................................................................. 95

3.2.3

Denormalized Numbers .......................................................................................... 96

3.3

Register Descriptions ...........................................................................................................97

3.3.1

Floating-Point Registers ......................................................................................... 97

3.3.2

Floating-Point Status/Control Register (FPSCR) ................................................... 98

3.3.3

Floating-Point Communication Register (FPUL) ................................................. 100

3.4

Rounding............................................................................................................................ 101

3.5

FPU Exceptions ................................................................................................................. 102

3.5.1

FPU Exception Sources ........................................................................................ 102

3.5.2

FPU Exception Handling ...................................................................................... 102

Section 4 Multi-Core Processor......................................................................... 105

4.1

Features.............................................................................................................................. 105

4.2

Register Descriptions ......................................................................................................... 106

4.2.1

CPU ID Register (CPUIDR)................................................................................. 107

4.2.2

Semaphore Registers 0 to 31 (SEMR0 to SEMR31) ............................................ 108

4.3

Operation ........................................................................................................................... 109

4.3.1

Initializing This LSI.............................................................................................. 109

4.3.2

Exclusive Control for CPUs ................................................................................. 110

Section 5 Clock Pulse Generator (CPG) ........................................................... 113

5.1

Features.............................................................................................................................. 113

5.2

Input/Output Pins...............................................................................................................117

5.3

Clock Operating Modes ..................................................................................................... 118

5.4

Register Descriptions ......................................................................................................... 123

5.4.1

Frequency Control Registers 0 and 1 (FRQCR0 and FRQCR1) .......................... 123

5.5

Changing the Frequency .................................................................................................... 128

5.5.1

Changing the Multiplication Rate ......................................................................... 128

5.5.2

Changing the Division Ratio................................................................................. 130

5.5.3

Notes on Changing the Multiplication Rate and Division Ratio........................... 131

5.6

Notes on Board Design ...................................................................................................... 132

5.6.1

Note on Inputting the External Clock ................................................................... 132

5.6.2

Note on Using a Crystal Resonator....................................................................... 132

5.6.3

Note on the Resonator........................................................................................... 133

5.6.4

Note on Using a PLL Oscillation Circuit.............................................................. 133

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