SH7205 datasheet(86/1904 Pages) RENESAS

86 / 1904 page

Section 2 CPU

Rev. 1.00 Mar. 25, 2008 Page 54 of 1868

REJ09B0372-0100

Table 2.4

T Bit

SH-2A CPU

Description

Example of Other CPU

CMP/GE

R1,R0

TRGET0

TRGET1

T bit is set when R0

≥ R1.

The program branches to TRGET0

when R0

≥ R1 and to TRGET1

when R0 < R1.

CMP.W

R1,R0

BGE

TRGET0

BLT

TRGET1

ADD

−1,R0

CMP/EQ

#0,R0

TRGET

T bit is not changed by ADD.

T bit is set when R0 = 0.

The program branches if R0 = 0.

SUB.W

#1,R0

BEQ

TRGET

(10) Immediate Data

Byte immediate data is located in an instruction code. Word or longword immediate data is not

located in instruction codes but in a memory table. The memory table is accessed by an immediate

data transfer instruction (MOV) using the PC relative addressing mode with displacement.

With the SH-2A, 17- to 28-bit immediate data can be located in an instruction code. However, for

21- to 28-bit immediate data, an OR instruction must be executed after the data is transferred to a

Table 2.5

Immediate Data Accessing

Classification

SH-2A CPU

Example of Other CPU

8-bit immediate

MOV

#H'12,R0

MOV.B

#H'12,R0

16-bit immediate

MOVI20

#H'1234,R0

MOV.W

#H'1234,R0

20-bit immediate

MOVI20

#H'12345,R0

MOV.L

#H'12345,R0

28-bit immediate

MOVI20S

#H'12345,R0

#H'67,R0

MOV.L

#H'1234567,R0

32-bit immediate

MOV.L

@(disp,PC),R0

.................

.DATA.L

H'12345678

MOV.L

#H'12345678,R0

Note:

@(disp, PC) accesses the immediate data.

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