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SH7205 Fiches technique(PDF) 72 Page - Renesas Technology Corp

No de pièce SH7205
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
PDF  1904 Pages
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Fabricant  RENESAS [Renesas Technology Corp]
Site Internet  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7205 Fiches technique(HTML) 72 Page - Renesas Technology Corp

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Section 1 Overview
Rev. 1.00 Mar. 25, 2008 Page 40 of 1868
REJ09B0372-0100
Classification
Symbol
I/O
Name
Function
FRB
I
Flash memory
ready/busy
Ready/busy: High level indicates
ready state and low level indicates
busy state.
FWE
O
Flash memory
write enable
Write enable: Flash memory latches
commands, addresses, and data on
the falling edge.
AND/NAND
flash memory
controller
(FLCTL)
NAF7 to NAF0
I/O
Flash memory
data
Data I/O pins.
DP1, DP0
I/O
USB D+ data
USB bus D+ data.
DM1, DM0
I/O
USB D– data
USB bus D– data.
VBUS
I
VBUS input
Connected to Vbus on USB bus.
REFRIN
I
Reference input
Connected to USBAPVss via
5.6
±1%-kΩ resistance.
USB_X1
I
USB_X2
O
Crystal resonator/
external clock for
USB
Connected to a crystal resonator for
USB. An external clock signal may
also be input to the USB_X1 pin.
USBAPVcc
I
Power supply for
transceiver
analog pins
Power supply for pins.
USBAPVss
I
Ground for
transceiver
analog pins
Ground for pins.
USBAVcc
I
Power supply for
transceiver
analog core
Power supply for core.
USBAVss
I
Ground for
transceiver
analog core
Ground for core.
USB2.0
host/function
module (USB)
USBDVcc
I
Power supply for
transceiver digital
core
Power supply for core.



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