SH7205 datasheet(16/1904 Pages) RENESAS

16 / 1904 page

Rev. 1.00 Mar. 25, 2008 Page xvi of xxxii

11.6

Suspending, Restarting, and Stopping of DMA Transfer .................................................. 439

11.6.1 Suspending and Restarting of DMA Transfer....................................................... 439

11.6.2 Stopping of DMA Transfer on Any Channel........................................................ 439

11.7

DMA Requests................................................................................................................... 440

11.7.1 DMA Request Sources.......................................................................................... 440

11.7.2 Synchronization Circuits for DMA Request Signal Inputs................................... 440

11.7.3 Sense Mode for DMA Requests ........................................................................... 442

11.8

Determination of DMA Channel Priorities ........................................................................ 445

11.8.1 Channel Priorities ................................................................................................. 445

11.8.2 Operation at Occurrence of Multiple DMA Requests........................................... 445

11.9

DMA Acknowledge Signal Output and DMA-Active Signal Output................................ 447

11.10 Units of Transfer and Transfer Byte Positions................................................................... 450

11.11 Reload Function.................................................................................................................451

11.12 Rotate Function.................................................................................................................. 453

11.13 Usage Note......................................................................................................................... 454

11.13.1 Note on Transition to Software Standby Mode or Deep Standby Mode............... 454

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)................................... 455

12.1

Features.............................................................................................................................. 455

12.2

Input/Output Pins...............................................................................................................460

12.3

Register Descriptions ......................................................................................................... 461

12.3.1 Timer Control Register (TCR).............................................................................. 465

12.3.2 Timer Mode Register (TMDR)............................................................................. 469

12.3.3 Timer I/O Control Register (TIOR) ...................................................................... 472

12.3.4 Timer Interrupt Enable Register (TIER)............................................................... 490

12.3.5 Timer Status Register (TSR)................................................................................. 493

12.3.6 Timer Buffer Operation Transfer Mode Register (TBTM)................................... 498

12.3.7 Timer Input Capture Control Register (TICCR)................................................... 499

12.3.8 Timer Synchronous Clear Register (TSYCR) ...................................................... 500

12.3.9 Timer A/D Converter Start Request Control Register (TADCR) ......................... 502

12.3.10 Timer A/D Converter Start Request Cycle Set Registers

(TADCORA_4 and TADCORB_4)...................................................................... 505

12.3.11 Timer A/D Converter Start Request Cycle Set Buffer Registers

(TADCOBRA_4 and TADCOBRB_4) ................................................................ 505

12.3.12 Timer Counter (TCNT)......................................................................................... 506

12.3.13 Timer General Register (TGR) ............................................................................. 506

12.3.14 Timer Start Register (TSTR) ................................................................................ 507

12.3.15 Timer Synchronous Register (TSYR)................................................................... 508

12.3.16 Timer Read/Write Enable Register (TRWER) ..................................................... 510

12.3.17 Timer Output Master Enable Register (TOER) .................................................... 511

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