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SH7205 Fiches technique(PDF) 96 Page - Renesas Technology Corp

No de pièce SH7205
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
PDF  1904 Pages
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Fabricant  RENESAS [Renesas Technology Corp]
Site Internet  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7205 Fiches technique(HTML) 96 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 1.00 Mar. 25, 2008 Page 64 of 1868
REJ09B0372-0100
Instruction Formats
Source
Operand
Destination
Operand
Example
iiiiiiii: Immediate
Indexed GBR
indirect
AND.B
#imm,@(R0,GBR)
iiiiiiii: Immediate
R0 (Register direct)
AND
#imm,R0
i format
xxxx
xxxx
iiii
15
0
iiii
iiiiiiii: Immediate
—
TRAPA
#imm
ni format
nnnn
iiii
xxxx
15
0
iiii
iiiiiiii: Immediate
nnnn: Register direct ADD
#imm,Rn
nnnn: Register direct
iii: Immediate
—
BLD
#imm3,Rn
ni3 format
xxxx
nnnn
xxxx
15
0
iii
x
—
nnnn: Register direct
iii: Immediate
BST
#imm3,Rn
ni20 format
iiii
iiii
iiii
iiii
15
0
xxxx
iiii
xxxx
nnnn
32
16
iiiiiiiiiiiiiiiiiiii:
Immediate
nnnn: Register direct MOVI20
#imm20, Rn
nnnndddddddddddd:
Register indirect with
displacement
iii: Immediate
—
BLD.B
#imm3,@(disp12,Rn
)
nid format
xxxx
dddd
dddd
dddd
15
0
xxxx
xiii
xxxx
nnnn
32
16
—
nnnndddddddddddd:
Register indirect with
displacement
iii: Immediate
BST.B
#imm3,@(disp12,Rn
)
Note:
*
In multiply-and-accumulate instructions, nnnn is the source register.



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