SH7205 datasheet(37/1904 Pages) RENESAS

No de pièce	SH7205

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

PDF	1904 Pages

Scroll/Zoom	100%

Fabricant	RENESAS [Renesas Technology Corp]

Site Internet	http://www.renesas.com

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37 / 1904 page

Section 1 Overview

Rev. 1.00 Mar. 25, 2008 Page 5 of 1868

REJ09B0372-0100

Items

Specification

Bus state controller

(BSC)

• Address space

 Six areas of CS0 to CS5 and SDRAM space, each a maximum of

64 Mbytes

 Data bus width selectable for each area (8, 16, or 32 bits)

 Cycle wait function: Up to 31 wait cycles (up to 7 cycles for page

access)

• Normal space interface

 Wait control:

Assertion/negation timing of chip select signals,

assertion/negation timing of read/write strobe signals,

start/end timing of data outputs, and

extension of chip select signals can be set

 Write access mode: 1-write strobe/byte-write strobe mode

 Page access mode: Page read/write supported (64-bit, 128-bit,

and 256-bit page sizes are available)

• SDRAM interface

 Up to two areas can be allocated as SDRAM space

(each area may be maximum of 64 Mbytes)

 Refreshing: Auto refresh (with internal programmable refresh

counter) or self refresh

 Access timing: Row-column latency, column latency, row-active

period can be set

 Initialization sequencer: Power-down, deep power-down, and

mode register setting functions

SH7205 Fiches technique(PDF) 37 Page - Renesas Technology Corp