SH7205 datasheet(34/1904 Pages) RENESAS

No de pièce	SH7205

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

PDF	1904 Pages

Scroll/Zoom	100%

Fabricant	RENESAS [Renesas Technology Corp]

Site Internet	http://www.renesas.com

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34 / 1904 page

Section 1 Overview

Rev. 1.00 Mar. 25, 2008 Page 2 of 1868

REJ09B0372-0100

Table 1.1

SH7205 Features

Items

Specification

CPU

• Renesas Technology original SuperH architecture

• Compatible with SH-1, SH-2, and SH-2E at object code level

• 32-bit internal data bus

• Support of an abundant register-set

 Sixteen 32-bit general registers

 Four 32-bit control registers

 Four 32-bit system registers

 Register bank for high-speed response to interrupts

• RISC-type instruction set (upward compatible with SH series)

 Instruction length: 16-bit fixed-length basic instructions for improved

code efficiency and 32-bit instructions for high performance and

usability

 Load/store architecture

 Delayed branch instructions

 Instruction set based on C language

• Superscalar architecture including an FPU that allows execution of two

instructions in parallel

• Instruction execution time: Up to two instructions/cycle

• Address space: 4 Gbytes

• Internal multiplier

• Five-stage pipeline

• Harvard architecture

SH7205 Fiches technique(PDF) 34 Page - Renesas Technology Corp