SH7205 datasheet(44/1904 Pages) RENESAS

44 / 1904 page

Section 1 Overview

Rev. 1.00 Mar. 25, 2008 Page 12 of 1868

REJ09B0372-0100

1.3

Block Diagram

SH-2A

CPU core

CPU0

BIU1

Cache controller

Instruction cache

memory (8 Kbytes)

Operand cache

memory (8 Kbytes)

On-chip RAM0

(high-speed)

64 Kbytes

High-speed on-chip

RAM0 access bus

CPU extension bus (I bus)

User break

controller

(UBC)

CPU bus

(C bus)

Internal CPU0 bus

Internal CPU1 bus

Internal DMA write bus

Internal DMA read bus

Floating-point

unit (FPU)

Bus bridge

CPU bus

(C bus)

Internal

bus

Port

UBCTRG

output

Peripheral bus 1

controller

SH-2A

CPU core

CPU1

Cache controller

Instruction cache

memory (8 Kbytes)

Operand cache

memory (8 Kbytes)

On-chip RAM1

(high-speed)

64 Kbytes

High-speed on-chip

RAM1 access bus

CPU extension bus (I bus)

User break

controller

(UBC)

CPU instruction fetch bus

(F bus)

CPU memory access bus

(M bus)

CPU instruction fetch bus

(F bus)

CPU memory access bus

(M bus)

Floating-point

unit (FPU)

Bus bridge

Peripheral bus 0

Port

A/D converter

(ADC)

D/A converter

(DAC)

User

debugging

interface

(H-UDI)

Power-down

mode

control

Port

I/O ports

Port

Clock pulse

generator

(CPG)

AT attachment

packet

interface

(ATAPI)

AT attachment

packet

interface I/O

Compare match

timer

(CMT)

Interrupt

controller

(INTC)

Multi-function

timer pulse

unit 2

(MTU2)

Watchdog

timer

(WDT)

Serial

communication

interface with

FIFO (SCIF)

I2C bus

interface 3

(IIC3)

RES input

MRES input

MMI input

IRQ input

PINT input

Realtime

clock

(RTC)

Synchronous

serial

commnication

unit (SSU)

General I/O

EXTAL input

XTAL output

CKIO I/O

Clock mode input

Timer pulse I/O

WDTOVF output

RTC_X1 input

RTC_X2 output

Serial I/O

I2C bus I/O

Analog input

ADTRG input

Analog output

Flash memory

I/F I/O

JTAG I/O

Pin function

controller

(PFC)

Controller

area

network

(RCAN-TL1)

On-chip RAM

(retention)

16 Kbytes

Serial I/O

Audio clock input

CAN bus I/O

AND/NAND

flash memory

controller

(FLCTL)

Serial sound

interface

with FIFO

(SSIF)

BIU3

BIU2

BIUE

Port

2D engine

(2DG)

Peripheral bus 3

controller

Peripheral bus 2

controller

Direct memory

access

controller

(DMAC)

USB2.0 host/

function module

(USB)

Bus state

controller

(BSC)

External bus I/O

External bus width mode input

USB bus I/O

USB clock input

(2 ports)

Video I/O

Peripheral bus 3

Peripheral bus 2

Peripheral bus 1

Expanded interface

for external bus access

DREQ input

DACK output

DACT output

TEND output

Port

BIU0

Peripheral bus 0

controller

Figure 1.1 Block Diagram

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