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SH7205 Fiches technique(PDF) 69 Page - Renesas Technology Corp |
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SH7205 Fiches technique(HTML) 69 Page - Renesas Technology Corp |
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69 / 1904 page ![]() Section 1 Overview Rev. 1.00 Mar. 25, 2008 Page 37 of 1868 REJ09B0372-0100 Classification Symbol I/O Name Function DREQ3 to DREQ0 I DMA-transfer request Input pins to receive external requests for DMA transfer. DACK3 to DACK0 O DMA-transfer request accept Output pins for signals indicating acceptance of external requests from external devices. DACT3 to DACT0 O DMA-transfer request active Output pins for signals indicating that DMA is active in response to external requests from external devices. Direct memory access controller (DMAC) TEND3 to TEND0 O DMA-transfer end output Output pins for DMA transfer end. TCLKA, TCLKB, TCLKC, TCLKD I MTU2 timer clock input External clock input pins for the timer. TIOC0A, TIOC0B, TIOC0C, TIOC0D I/O MTU2 input capture/output compare (channel 0) The TGRA_0 to TGRD_0 input capture input/output compare output/PWM output pins. TIOC1A, TIOC1B I/O MTU2 input capture/output compare (channel 1) The TGRA_1 and TGRB_1 input capture input/output compare output/PWM output pins. TIOC2A, TIOC2B I/O MTU2 input capture/output compare (channel 2) The TGRA_2 and TGRB_2 input capture input/output compare output/PWM output pins. TIOC3A, TIOC3B, TIOC3C, TIOC3D I/O MTU2 input capture/output compare (channel 3) The TGRA_3 to TGRD_3 input capture input/output compare output/PWM output pins. Multi-function timer pulse unit 2 (MTU2) TIOC4A, TIOC4B, TIOC4C, TIOC4D I/O MTU2 input capture/output compare (channel 4) The TGRA_4 and TGRB_4 input capture input/output compare output/PWM output pins. |
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