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SH7205 Fiches technique(PDF) 21 Page - Renesas Technology Corp

No de pièce SH7205
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
PDF  1904 Pages
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Fabricant  RENESAS [Renesas Technology Corp]
Site Internet  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7205 Fiches technique(HTML) 21 Page - Renesas Technology Corp

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Rev. 1.00 Mar. 25, 2008 Page xxi of xxxii
16.6
Usage Notes ....................................................................................................................... 795
16.6.1 SCFTDR Writing and TDFE Flag ........................................................................ 795
16.6.2 SCFRDR Reading and RDF Flag ......................................................................... 795
16.6.3 Restriction on DMAC Usage ................................................................................ 796
16.6.4 Break Detection and Processing ........................................................................... 796
16.6.5 Sending a Break Signal......................................................................................... 796
16.6.6 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) ...... 796
16.6.7 Selection of Base Clock in Asynchronous Mode.................................................. 798
Section 17 Synchronous Serial Communication Unit (SSU) ............................799
17.1
Features.............................................................................................................................. 799
17.2
Input/Output Pins ...............................................................................................................801
17.3
Register Descriptions ......................................................................................................... 802
17.3.1 SS Control Register H (SSCRH) .......................................................................... 803
17.3.2 SS Control Register L (SSCRL) ........................................................................... 805
17.3.3 SS Mode Register (SSMR) ................................................................................... 806
17.3.4 SS Enable Register (SSER) .................................................................................. 807
17.3.5 SS Status Register (SSSR) .................................................................................... 808
17.3.6 SS Control Register 2 (SSCR2) ............................................................................ 812
17.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)................................... 813
17.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3) .................................... 814
17.3.9 SS Shift Register (SSTRSR) ................................................................................. 815
17.4
Operation ........................................................................................................................... 816
17.4.1 Transfer Clock ...................................................................................................... 816
17.4.2 Relationship of Clock Phase, Polarity, and Data .................................................. 816
17.4.3 Relationship between Data Input/Output Pins and Shift Register ........................ 817
17.4.4 Communication Modes and Pin Functions ........................................................... 819
17.4.5 SSU Mode............................................................................................................. 821
17.4.6
SCS Pin Control and Conflict Error...................................................................... 830
17.4.7 Clock Synchronous Communication Mode .......................................................... 831
17.5
SSU Interrupt Sources and DMAC .................................................................................... 838
17.6
Usage Note......................................................................................................................... 839
17.6.1 Module Standby Mode Setting ............................................................................. 839
17.6.2 Consecutive Data Transmission/Reception in SSU Slave Mode .......................... 839
Section 18 I
2C Bus Interface 3 (IIC3) ................................................................841
18.1
Features.............................................................................................................................. 841
18.2
Input/Output Pins ...............................................................................................................843
18.3
Register Descriptions ......................................................................................................... 844
18.3.1 I
2C Bus Control Register 1 (ICCR1)..................................................................... 845



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