| Moteur de recherche de fiches techniques de composants électroniques |
|
STLC5466 Fiches technique(PDF) 104 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STLC5466 Fiches technique(HTML) 104 Page - STMicroelectronics |
|
104 / 130 page ![]() STLC5466 104/130 Figure 1-27: MHDLC clock generation FRAME A CLOCK A FRAME B CLOCK B Select A or B INT1 RESET Supervision Deactivation FSCGCI FSCV* SYN1 SYN0 Frame Clock HCL CLOCK SELECTION CLOCK ADAPTATION Ref. Clock To the internal A or B Selected DCLK (SELB) (BSEL) MHDLC (CSD) Clock General Configuration Register (GCR) Clock Lack Detection from 250m s At RESET FRAME A and CLOCK A are selected |
|
Lien URL |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Lien vers la fiche technique | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |