STLC5466 datasheet(49/130 Pages) STMICROELECTRONICS

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STLC5466

: Flag Monitoring

This bit is a status bit read by the microprocessor.

FM=1: HDLC Controller is receiving a frame or HDLC Controller has just received one flag.

FM is put to 0 by the microprocessor.

CRC

: CRC stored in external memory

CRC = 1, the CRC is stored at the end of the frame in external memory.

CRC = 0, the CRC is not stored into external memory.

AR10

: Address Recognition10

AR10 = 1, First byte after opening flag of received frame is compared to AF0/7 bits of AFRDR.

If the first byte received and AF0/7 bits are not identical the frame is ignored.

AR10 = 0, First byte after opening flag of received frame is not compared to AF0/7 bits of

AFRDR Register.

AR11

: Address Recognition 11

AR11 = 1, First byte after opening flag of received frame is compared to all “1”s.If the first byte

received is not all “1”s the frame is ignored.

AR11 = 0, First byte after opening flag of received frame is not compared to all “1”s.

AR20

: Address Recognition 20

AR20 = 1, Second byte after opening flag of received frame is compared to AF8/15 bits of

AFRDR Register. If the second byte received and AF8/15 bits are not identical the frame is ig-

nored.

AR20 = 0, Second byte after opening flag of received frame is not compared to AF8/15 bits of

AFRDR Register.

AR21

: Address Recognition 21

AR21 = 1, Second byte after opening flag of received frame is compared to all “1”s. If the Sec-

ond byte received is not all “1”s the frame is ignored.

AR21 = 0, Second byte after opening flag of received frame is not compared to all “1”s.

Second Byte

First Byte

Conditions to Receive a Frame

AR21

AR20

AR11

AR10

Each frame is received without condition.

Only value of the first received byte must be equal to that of AF0/7 bits.

Only value of the first received byte must be equal to all “1”s.

The value of the first received byte must be equal either to that of AF0/7 or to all

“1”s.

Only value of the second received byte must be equal to that of AF8/15 bits.

The value of the first received byte must be equal to that of AF0/7 bits and the

value of the second received byte must be equal to that of AF8/15 bits.

The value of first received byte is must be equal to all “1”s and the value of sec-

ond received byte must be equal to that of AF8/15 bits.

The value of the first received byte must be equal either to that of AF0/7 or to all

“1”s and the value of the second received byte must be equal to that of AF8/15

bits.

Only the value of the second received byte must be equal to all “1”s.

The value of the first received byte must be equal to that of AF0/7 bits and the

value of the second received byte must be equal to all “1”s.

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