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STLC5466 Fiches technique(PDF) 71 Page - STMicroelectronics |
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STLC5466 Fiches technique(HTML) 71 Page - STMicroelectronics |
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71 / 130 page ![]() 71/130 STLC5466 VII - EXTERNAL REGISTERS These registers are located in shared memory. Initiate Block Address Registers (IBAR1 and IBAR2) give respectively the Initiate Block Address (IBA1 and IBA2) in shared memory. From IBA1 the different addresses are obtained: • Initialization Block address concerning the first HDLC Controller (HDLC1) • HDLC interrupt Queue for the first HDLC Controller (HDLC1) and the second (HDLC2) • MON interrupt Queue • C/I interrupt Queue From IBA1 only the following address is obtained: • Initialization Block address concerning the second HDLC Controller (HDLC2) ‘Not used’ bits (Nu) are accessible by the microprocessor but the use of these bits by software is not rec- ommended. VII.1 - Initialization Block in External Memory (IBA1 and IBA2) When Direct Memory Access Controller receives START from one of 64 channels, it reads initialization block immediately to know the first address of the first descriptor for this channel. Bit 0 of Transmit Descriptor Address (TDA Low) and bit 0 of Receive Descriptor Address (RDA Low), are at ZERO mandatory. This Least Significant Bit is not used by DMA Controller, the shared memory is al- ways a 16 bit memory for the DMA Controller. The Receive Descriptor Address (RDA) is never modified by the RX DMA Controller in this Initialization Block N.B. If several descriptors are used to transmit the current frame then before transmitting frame, TX DMA Controller stores the address of the first Transmit Descriptor Address (TDA) into this Initialization Block if BOF bit is at “1” (See Transmit Descriptor). Descriptor Address Channel Address bit15 bit8 bit7 bit0 CH 0 T IBA+00 Not used TDA High IBA+02 Transmit Descriptor Address (TDA Low) R IBA+04 Not used RDA High IBA+06 Receive Descriptor Address (RDA Low) CH1 T IBA+08 Not used TDA High IBA+10 Transmit Descriptor Address (TDA Low) R IBA+12 Not used RDA High IBA+14 Receive Descriptor Address (RDA Low) CH 2 to CH30 IBA+16 to IBA+246 CH 31 T IBA+248 Not used TDA High IBA+250 Transmit Descriptor Address (TDA Low) R IBA+252 Not used RDA High IBA+254 Receive Descriptor Address (RDA Low) |
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