STLC5466 datasheet(2/130 Pages) STMICROELECTRONICS

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STLC5466

2/130

TABLE OF CONTENTS

PIN INFORMATION................................................................................................................6

I.1

PIN CONNECTIONS ..............................................................................................................6

I.2

PIN DESCRIPTION ................................................................. ..............................................7

I.3

PIN DEFINITION...................................................................... ............................................12

I.3.1

Input Pin Definition................................................................................................................12

I.3.2

Output Pin Definition ............................................................................................................12

I.3.3

Input/Output Pin Definition. ..................................................................................................12

BLOCK DIAGRAM ...............................................................................................................13

III

FUNCTIONAL DESCRIPTION .............................................................................................13

III.1

THE SWITCHING MATRIX N X 64 KBITS/S........................................................................13

III.1.1

Function Description .............................................................................................................13

III.1.2

Architecture of the Matrix .....................................................................................................13

III.1.3

Connection Function ............................................................................................................13

III.1.4

Loop Back Function .............................................................................................................15

III.1.5

Delay through the Matrix ......................................................................................................15

III.1.5.1

Variable Delay Mode ........................................................................................................15

III.1.5.2

Sequence Integrity Mode ..................................................................................................15

III.1.6

Connection Memory .............................................................................................................15

III.1.6.1

Description .......................................................................................................................15

III.1.6.2

Access to Connection Memory .........................................................................................15

III.1.6.3

Access to Data Memory....................................................................................................15

III.1.7

Switching at 32 Kbit/s ...........................................................................................................15

III.1.8

Switching at 16 Kbit/s ...........................................................................................................16

III.2

HDLC CONTROLLER.............................................................. ............................................16

III.2.1

Function description .............................................................................................................16

III.2.1.1

Format of the HDLC Frame ..............................................................................................16

III.2.1.2

Composition of an HDLC Frame .......................................................................................16

III.2.1.3

Description and Functions of the HDLC Bytes..................................................................16

III.2.2

CSMA/CR Capability ............................................................................................................17

III.2.3

Time Slot Assigner Memory .................................................................................................17

III.2.4

Data Storage Structure .........................................................................................................18

III.2.4.1

Reception..........................................................................................................................18

III.2.4.2

Transmission.....................................................................................................................18

III.2.4.3

Frame Relay .....................................................................................................................18

III.2.5

Transparent Modes ..............................................................................................................18

III.2.6

Command of the HDLC Channels ........................................................................................19

III.2.6.1

Reception Control .............................................................................................................19

III.2.6.2

Transmission Control ........................................................................................................19

III.3

C/I AND MONITOR.................................................................. ............................................19

III.3.1

Function Description ............................................................................................................19

III.3.2

GCI and V* Protocol .............................................................................................................19

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