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STLC5466 Fiches technique(PDF) 101 Page - STMicroelectronics |
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STLC5466 Fiches technique(HTML) 101 Page - STMicroelectronics |
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101 / 130 page ![]() 101/130 STLC5466 1.3.0.1 Memory obtained with 8M x 8 SDRAM circuit: The Address bits delivered by the Multi-HDLC for 8M x n SDRAM circuits are: ADM12/13 for Bank select corresponding with A22/23 delivered by the µP ADM0/11 for Row address inputs corresponding with A10/21 delivered by the µP ADM0/8 for Column address inputs corresponding with A1/9 delivered by the µP Figure 1-24: Second example, 8Mx16 SDRAM memory organisation Signals A0 NLDS NUDS UDQM 1 0 1 LDQM 0 1 0 8M x 16 with 2 circuits NCE LDQM 0 1 DM0/7 DM8/15 UDQM ADM0/13, NCE, NWE, NRAS, NCAS, MCLK are connected to each circuit 8M x 8 circuit: four banks 2Mbytes by bank |
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