STLC5466 datasheet(68/130 Pages) STMICROELECTRONICS

68 / 130 page

STLC5466

68/130

VI.41 - Fill Character Register 2

FCR2 (60)H

VI.42 - SDRAM Mode Register

SDRAMR (72)H

When the microprocessor writes in this SDRAM Mode register, the SDRAM controller initializes the

SDRAM if the NINIT bit of GCR2 is at 0.

When the microprocessor reads this register, the SDRAM controller is not affected.

Some parameters are frozen:

The option field is: Burst Read and Single Write.

The Burst Length is 4.

The burst data is addressed in sequential mode

The programmable parameters are:

The 12-bit word sent by the Multi-HDLC to initialize the SDRAM is:

For information:

bit15

bit8

bit7

bit0

FC7

FC6

FC5

FC4

FC3

FC2

FC1

FC0

After reset (0000)H

FC0/7

: FILL CHARACTER (eight bits)

In Transparent Mode M1, two messages are separated by FILL CHARACTERS and the de-

tection of one FILL CHARACTER marks the end of a message.

bit15

bit8

bit7

bit5

bit4

bit0

NuNuNuNuNuNu

LT1

LT0

NuNuNuNu

After reset (0030)H

LT0/1 :

Latency Mode

Three configurations are possible: NCAS Latency can be 1, 2 or 3)

bit15

bit11

bit8

bit7

bit5

bit4

bit0

LT2

LT1

LT0

BL2

BL1

BL0

LT1

LT0

Option field: Burst Read and Single Write

Latency mode

Wrap type

Burst Length

LT2

LT1

LT0

BL2

BL1

BL0

LT1

LT0

NCAS Latency

Not allowed

STLC5466 Fiches technique(PDF) 68 Page - STMicroelectronics

STLC5466 Fiches technique(HTML) 68 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Fiches technique Télécharger

Lien URL