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STLC5466 Fiches technique(PDF) 59 Page - STMicroelectronics |
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STLC5466 Fiches technique(HTML) 59 Page - STMicroelectronics |
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59 / 130 page ![]() 59/130 STLC5466 VI.31 - Timer Register 1 TIMR1 (3C)H This programmable register indicates the time at the end of which the Watch Dog delivers logic “1” on the pin WDO (which is an output) but only if the microprocessor does not reset the counter assigned (with the help of WDR bit of IDCR (Identification and Dynamic Command Register) during the time defined by the Timer Register.When the microprocessor does not reset the counter, the pin WDO delivers logic “1 as soon as delta T plus programmed time are reached. (delta T from one to two clock periods of the associ- ated counter). Remark: the time indicated in this register is obtained when the clock period of the associated counter is 250 mi- croseconds. The minimum programmable time is four clock periods (1 millisecond in this case); the dura- tion of the pulse delivered by the pin WDO is one clock period (250 microseconds). The Timer Register and its counter can be used as a time base by the microprocessor. An interrupt (TIM) is generated at each period defined by the Timer Register if the microprocessor does not reset the counter. To reset the counter, WDR (bit of IDCR) must be set to “1” by the microprocessor. The Watch Dog or the Timer is incremented by the Frame Synchronisation clock divided by two (TBFS=1) or by a submultiple of MCLK signal (TBFS=0; TBFS, bit of Interrupt Queue Size Register). Example: TBFS=1 if the Frame Synchronisation clock is at 8 kHz, the period of the counter clock is 250 microsec- onds TBFS=0 if MCLK clock is at 32768 kHz the clock period of the counter is 250 microseconds (inverse of 32768kHz divided by 8192). When TSV=1{bit of General Configuration Register)} this programmable register (TIMR1) is not signifi- cant. VI.32 - Test Register TR (3E)H bit15 bit8 bit7 bit0 S3 S2 S1 S0 MS9 MS8 MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0 MM1 MM0 0 to 5s 0 to 999ms 0 to 3x0.25ms After reset (0800)H bit15 bit8 bit7 bit0 re s e rv e d re s e r v e d T15/0 : Test bits 0/15 These bits are reserved for the test of the circuit in production.The use of these bits is forbidden. |
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