STLC5466 datasheet(72/130 Pages) STMICROELECTRONICS

72 / 130 page

STLC5466

72/130

VII.2 - Receive Descriptor

This receive descriptor is located in shared memory. The quantity of descriptors is limited by the memory

size only.

The 5 first words located in shared memory to RDA+00 from RDA+08 are written by the microprocessor

and read by the DMAC only. The 6th word located in shared memory in RDA+10 is written by the DMAC

only during the frame reception and read by the microprocessor.

VII.2.1 - Bits written by the Microprocessor only

VII.2.2 - Bits written by the Rx DMAC only

9876543210

RDA+00

SIM

IBC

EOQ

Size Of the Buffer (SOB)

RDA+02

Not used

RBA High (8 bits)

RDA+04

Receive Buffer Address Low (16 bits)

RDA+06

Not used

NRDA High (8 bits)

RDA+08

Next Receive Descriptor Address Low (16 bits)

RDA+10

ABT

OVF

FCR

Number of Bytes Received (NBR)

SOB

: Size Of the Buffer associated to descriptor. These 12bits allows to reach 4096 bytes).

If SOB = 0, DMAC goes to next descriptor.

RBA

: Receive Buffer Address. LSB of RBA Low is at Zero mandatory.

RDA

: Receive Descriptor Address.

NRDA : Next Receive Descriptor Address. LSB of NRDA Low is at Zero mandatory.

NBR

: Number of Bytes Received (up to 4096).

IBC

: Interrupt if the buffer has been completed.

IBC=1, the DMAC generates an interrupt if the buffer has been completed.

EOQ

: End Of Queue.

EOQ=1, the DMAC stops immediately its reception generates an interrupt (HDLC = 1 in IR) and

waits a command from the HRCR (HDLC Receive Command Register).

EOQ=0, the DMAC continues.

SIM

Signal Interrupt Mask

SIM=1, when an event occurs the RX DMAC thanks to Interrupt controller stores the features of

this event in the HDLC Interrupt Queue but the Interrupt Register is not written. So there is no

interrupt signal on INT0 pin.

SIM=0, when an event occurs the RX DMAC thanks to Interrupt controller stores the features of

this event in the Interrupt Queue and the HDLC bit of the Interrupt Register is put at “1”. So INT0

pin goes to Vcc if HDLC bit is not masked.

ABT

OVF

FCRC

Definition

The frame has been received without error. The end of frame is in this buffer.

The frame has been received with false CRC.

If NBR is different to 0, the buffer related to this descriptor is completed.The end

of frame is not in this buffer.

If NBR is equal to 0, the Rx DMAC is receiving a frame.

STLC5466 Fiches technique(PDF) 72 Page - STMicroelectronics

STLC5466 Fiches technique(HTML) 72 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Fiches technique Télécharger

Lien URL