STLC5466 datasheet(52/130 Pages) STMICROELECTRONICS

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STLC5466

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VI.20 - GCI Channels Definition Register 2

GCIR2 (26)H

For definition see GCI Channels Definition Register above.

VI.21 - GCI Channels Definition Register 3

GCIR3 (28)H

For definition see GCI Channels Definition Register above.

VI.22 - Transmit Command / Indicate Register

TCIR (2A)H

When this register is written by the microprocessor, these different bits mean:

bit15

bit8

bit7

bit0

ANA51 VCI51 V*51 VM51 ANA50 VCI50 V*50 VM50 ANA41 VCI41 V*41 VM41 ANA40 VCI40 V*40 VM40

TDM5

TDM4

TDM5

TDM4

GCI CHANNEL 5

GCI CHANNEL 6

After reset (0000)H

bit15

bit8

bit7

bit0

ANA71 VCI71 V*71 VM71 ANA70 VCI70 V*70 VM70 ANA61 VCI61 V*61 VM61 ANA60 VCI60 V*60 VM60

TDM5

TDM4

TDM5

TDM4

GCI CHANNEL 7

GCI CHANNEL 8

After reset (0000)H

bit15

bit8

bit7

bit0

CA2

CA1

CA0

READ

C6/A

C5/E C4/S1 C3S2 C2S3 C1S4

After reset (00FF)H

READ

: READ C/I MEMORY

READ = 1, READ C/I MEMORY.

READ = 0, WRITE C/I MEMORY.

CA 0/2 : TRANSMIT COMMAND/INDICATE MEMORY ADDRESS

CA0/2: These bits define one of eight Command/Indicate Channels.

: This bit defines one of two GCI multiplexes.

G0 = 0, TDM4 is selected.

G0 = 1, TDM5 is selected.

C6/1

: New Primitive to be transmitted

C6 is transmitted first if ANA = 1.

C4 is transmitted first if ANA = 0.

: Destination; this bit defines the destination of bit 0 to 5.

D=0: the primitive C6 to C1 is transmitted directly into GCI channel defined by G0 and CA 0/2

D=1: the 6 bit word A, E, S1, S2, S3, S4 is put instead of the six bits received latest during the

timeslot 4n+3 (GCI channel defined by G0 and CA 0/2) and transmitted into any selected out-

put timeslot after switching.

bit15

bit8

bit7

bit0

D=0

CA2

CA1

CA0

READ

NuNuC6C5C4C3C2C1

D=1

CA2

CA1

CA0

READ

C6/1

: New Primitive to be transmitted to the selected GCI channel (DOUT4 or DOUT5)

A, E,

S1 to S4

New 6 bit word to be transmitted into any output timeslot.

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