STLC5466 datasheet(42/130 Pages) STMICROELECTRONICS

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STLC5466

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– The IM2/1 bits of Source Register (SRCR of CMDR) indicate the DIN pin number and

the OM2/1 bits of Destination Register (DSTR of CMAR) indicate the Dout pin number

– The ITS4/0 and IM0 bits of Source Register (SRCR of CMDR) indicate the input timeslot number. (IM0

bit is the Least Significant Bit; it indicates either even timeslot or odd timeslot.

– The OTS4/0 and OM0 bits of Destination Register (DSTR of CMAR) indicate the output timeslot number.

(OM0 bit is the Least Significant Bit; it indicates either even timeslot or odd timeslot.

• Nota Bene:

CLOCK A/B is at 4 or at 8 MHz in accordance with HCL bit of General Configuration Register GCR (02).

– HCL=1, bit clock frequency is at 8 192 kHZ.

For a TDM at 4 Mbit/s or 2Mbit/s, each received bit is sampled at 3/4 bit-time.

IM2 (bit7)

IM1 (bit6)

DIN pin

OM2 (bit7)

OM1 (bit6)

DOUT pin

DIN0

DOUT0

DIN2

DOUT2

DIN4

DOUT4

DIN6

DOUT6

ITS4

(bit4)

ITS3

(bit3)

ITS2

(bit2)

ITS1

(bit1)

ITS0

(bit0)

IM0

(bit5)

Input timeslot

number

OTS4

(bit4)

OTS3

(bit3)

OTS2

(bit2)

OTS1

(bit1)

OTS0

(bit0)

OM0

(bit5)

Output timeslot

number

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