STLC5466 datasheet(44/130 Pages) STMICROELECTRONICS

44 / 130 page

STLC5466

44/130

ACCESS MODE REGISTER (AMR)

READ : READ MEMORY

READ = 1, Read Connection Memory (or Data Memory in accordance with CM).

READ = 0, Write Connection Memory.

: CONNECTION MEMORY

CM = 1, Write or Read Connection Memory in accordance with READ.

CM = 0, Read only Data Memory (READ = 0 has no effect).

N.B. After software reset (bit 2 of IDCR Register) or pin reset the automate of the Connection

Memory is launched. This automate initializes the Connection Memory within 250 microsec-

onds at the most. This automate is stopped when the microprocessor writes (0200H) in CMAR

BID

: BIDIRECTIONNAL CONNECTION.

BID = 1; Two connections are set up:

• ITSx ITDMp ------> OTSy OTDMq (LOOP of CMDR Register is taken into account) and

• ITSy ITDMq ------> OTSx OTDMp (LOOP of CMDR Register is not taken into account).

BID = 0; One connection is set up:

• ITSx ITDMp ------> OTSy OTDMq only.

CAC

: CYCLICAL ACCESS

CAC = 1 (BID is ignored)

if Write Connection Memory, an automatic data write from Connection Memory Data Register

(CMDR) up to 256 locations of Connection Memory occurs. The first address is indicated by the

if Read Connection Memory, an automatic transfer of data from the location indicated by the

processor occurs. The last location is (FF)H.

CAC = 0, Write and Read Connection Memory in the normal way.

• N.B. After software reset (bit 2 of IDCR Register) or pin reset an automate is working to reset the con-

nection memory (all “0”). The automate is stopped when the microprocessor writes TAAR Register with

CAC= 0.

CACL : CYCLICAL ACCESS LIMITED

CACL = 1(BID is ignored)

If Write Connection Memory, an automatic data write from Connection Memory Data Register

(CMDR) up to 32 locations of Connection Memory occurs. The first location is indicated by OTS

0/4bits of the register (DSTR) related to OTDMq as defined by OM0/2 occurs. The last location

is q +1 F(H).

If Read Connection Memory, an automatic transfer of data from Connection Memory into Con-

nection Memory Data Register (CMDR) after reading this last by the microprocessor oc-

curs.The first location is indicated by OTS 0/4 bits of the register (DSTR) related to OTDMq as

defined by OM0/2. The last location is q +1 F(H).

CACL = 0, Write and Read Connection Memory in the normal way.

: Transparent Connection

TC = 1, (BID is ignored) if READ = 0:

CAC = 0 and CACL = 0. The DSTR bits are taken into account instead of SRCR bits. SRCR

bits are ignored (Destination and Source are identical). The contents of Input time slot i - Input

multiplex j is switched into Output time slot i - Output multiplex j.

CAC = 0 and CACL = 1. Up to 32 “Transparent Connections” are set up.

CAC = 1 and CACL = 0. Up to 256 “Transparent Connections” are set up.

TC = 0, Write and Read Connection Memory in accordance with BID.

STLC5466 Fiches technique(PDF) 44 Page - STMicroelectronics

STLC5466 Fiches technique(HTML) 44 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Fiches technique Télécharger

Lien URL