STLC5466 datasheet(17/130 Pages) STMICROELECTRONICS

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STLC5466

– BIT STUFFING AND UNSTUFFING

This operation is done to avoid the confusion of

a data byte with a flag.

In transmission, if five consecutive 1’s appear in

the serial stream being transmitted, a zero is au-

tomatically inserted (bit stuffing) after the fifth

“1”.

In reception, if five consecutive “1” followed by a

zero are received, the “0” is assumed to have

been inserted and is automatically deleted (bit

unstuffing).

– FRAME CHECK SEQUENCE

The Frame Check Sequence is calculated ac-

cording to the recommendation Q921 of the

CCITT.

– ADDRESS RECOGNITION

In the frame, one or two bytes are transmitted to

indicate the destination of the message. Two

types of addresses are possible:

- a specific destination address

- a broadcast address.

In reception, the controller compares the receive

addresses to internal registers, which contain

the address message. 4 bits in the receive com-

mand register (HRCR) inform the receiver of

which registers, it has to take into account for the

comparison. The receiver compares the two ad-

dress bytes of the message to the specific board

address and the broadcast address. Upon an

address match, the address and the data follow-

ing are written to the data buffers; upon an ad-

dress mismatch, the frame is ignored. So, it

authorizes the filtering of the messages. If no

comparison is specified, each frame is received

whatever its address field.

In Transmission, the controller sends the frame

including the destination or broadcast address-

es.

III.2.2 - CSMA/CR Capability

An HDLC channel can come in and go out by any

TDM input on the matrix.

For time constraints, direct HDLC Access is

achieved by the input TDM (DIN 8 for the first

HDLC controller and DIN9 for the second HDLC

controller) and the output TDM (DOUT6 for the

first and DOUT7 for the second HDLC controller).

In transmission, a time slot of a TDM can be

shared between different sources in Multi-point to

point configuration (different subscriber’s boards

for example). The arbitration system is the CSMA/

CR (Carrier Sense Multiple access with Conten-

tion Resolution).

The contention is resolved by a bus connected to

the CB1 pin (Contention Bus) for the first HDLC

controller and CB2 pin for the second HDLC con-

troller. These two bus are respectively a 2Mbit/s

wire line common to all the potential sources.

If the first HDLC controller (or the second) has ob-

tained the access to the bus, the data to transmit

is sent simultaneously on the CB1 line (or the CB2

line) and the output TDM. The result of the conten-

tion is read back on the Echo line (EC1or EC2). If

a collision is detected, the transmission is stopped

immediately. A contention on a bit basis is so

achieved. Each message to be sent with CSMA/

CR has a priority class (PRI = 8, 10) indicated by

the Transmit Descriptor and some rules are imple-

mented to arbitrate the access to the line. The

CSMA/CR Algorithm is given. When a request to

send a message occurs, the transmitter deter-

mines if the shared channel is free. The

Multi-

HDLC listens to the Echo line. If C or more consec-

utive “1” are detected (C depending on the mes-

sage’s priority), the Multi-HDLC begins to send its

message. Each bit sent is sampled back and com-

pared with the original value to send. If a bit is dif-

ferent,

the

transmission

instantaneously

stopped (before the end of this bit time) and will re-

start as soon as the Multi-HDLC will detect that the

channel is free without interrupting the microproc-

essor.

After a successful transmission of a message, a

programmable penalty PEN(1 or 2) is applied to

the transmitter. It guarantees that the same trans-

mitter will not take the bus another time before a

transmitter which has to send a message of same

priority.

In case of a collision, the frame which has been

aborted is automatically retransmitted by the DMA

controller without warning the microprocessor of

this collision. The frame can be located in several

buffers in external memory. The collision can be

detected from the second bit of the opening frame

to the last but one bit of the closing frame.

III.2.3 - Time Slot Assigner Memory

Each HDLC channel is bidirectional and is defined

by two Time Slot Assigners (TSA).

TSA is a memory of 32 words (one per physical

Time Slot) where all of the 32 input and output time

slots of the HDLC controllers can be associated to

logical HDLC channels. Super channels are creat-

ed by assigning the same logical channel number

to several physical time slots.

The following features are programmed for each

HDLC time slot:

– Time slot used or not

– One logical channel number

– Its source:

- DIN 8 or the output 7 of the matrix for the first

Time Slot Assigner

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