STLC5466 datasheet(40/130 Pages) STMICROELECTRONICS

40 / 130 page

STLC5466

40/130

Table: switching at 16 Kb/s when ITS3=1

ITS3 ITS2 ITSI ITS 0 Upstream

Source: D channels of one GCI

channel

Destination: two bits of one TDM

Downstream

Source: two bits of one TDM

Destination: D channels of one

GCI channel

The contents of D channels of

GCI 0 /3 of multiplex DIN4 are

transferred into the output times-

lot of one TDM defined by the

destination register (CMAR).

D channel of GCI 0 in bit 7/8

D channel of GCI 1 in bit 5/6

D channel of GCI 2 in bit 3/4

D channel of GCI 3 in bit 1/2

The contents of the input times

lot

(same

number

the

number of the output timeslot) is

transferred in D channel of GCI

0/3 of multiplex DOUT4

bit 7/8 in D channel of GCI 0

bit 5/6 in D channel of GCI 1

bit 3/4 in D channel of GCI 2

bit 1/2 in D channel of GCI 3

The contents of D channels of

GCI 4/7 of multiplex DIN4 are

transferred into the output times-

lot of one TDM defined by the

destination register (CMAR).

D channel of GCI 4 in bit 7/8

D channel of GCI 5 in bit 5/6

D channel of GCI 6 in bit 3/4

D channel of GCI 7 in bit 1/2

The contents of the input times

lot

(same

number

the

number of the output timeslot) is

transferred in D channel of GCI

4/7 of multiplex DOUT4.

bit 7/8 in D channel of GCI 4

bit 5/6 in D channel of GCI 5

bit 3/4 in D channel of GCI 6

bit 1/2 in D channel of GCI 7

The contents of D channels of

GCI 0 /3 of multiplex DIN5 are

transferred into the output times-

lot of one TDM defined by the

destination register (CMAR).

D channel of GCI 0 in bit 7/8

D channel of GCI 1 in bit 5/6

D channel of GCI 2 in bit 3/4

D channel of GCI 3 in bit 1/2

The contents of the input times

lot (same number as the

number of the output timeslot)

is transferred in D channel of

GCI 0/3 of multiplex DOUT5.

bit 7/8 in D channel of GCI 0

bit 5/6 in D channel of GCI 1

bit 3/4 in D channel of GCI 2

bit 1/2 in D channel of GCI 3

The contents of D channels of

GCI 4/7 of multiplex DIN5 are

transferred into the output times-

lot of one TDM defined by the

destination register (CMAR).

D channel of GCI 4 in bit 7/8

D channel of GCI 5 in bit 5/6

D channel of GCI 6 in bit 3/4

D channel of GCI 7 in bit 1/2

The contents of the input times-

lot

(same

number

the

number of the output timeslot) is

transferred in D channel of GCI

4/7 of multiplex DOUT5.

bit 7/8 in D channel of GCI 4

bit 5/6 in D channel of GCI 5

bit 3/4 in D channel of GCI 6

bit 1/2 in D channel of GCI 7

PRSA :S Pseudo Random Sequence analyser

If PRSA = 1, PRS analyser is enabled during OTSy OTDMq and receives data:

S0 = 0, data comes from Data Memory.

S0 = 1 AND S1 = 1, Data comes from PRS Generator (Test Mode).

If PRSA = 0, PRS analyser is disabled during OTSy OTDMq.

STLC5466 Fiches technique(PDF) 40 Page - STMicroelectronics

STLC5466 Fiches technique(HTML) 40 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Fiches technique Télécharger

Lien URL