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EMC2302 Fiches technique(PDF) 37 Page - SMSC Corporation

No de pièce EMC2302
Description  Dual RPM-Based PWM Fan Controller
PDF  44 Pages
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Fabricant  SMSC [SMSC Corporation]
Site Internet  http://www.smsc.com
Logo SMSC - SMSC Corporation

EMC2302 Fiches technique(HTML) 37 Page - SMSC Corporation

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Dual RPM-Based PWM Fan Controller
Datasheet
SMSC EMC2302
37
Revision 1.1 (10-12-09)
DATASHEET
5.16
Fan Drive Fail Band Registers
The Fan Drive Fail Band Registers store the number of tach counts used by the Fan Drive Fail
detection circuitry. This circuitry is activated when the fan drive setting high byte is at FFh. When it is
enabled, the actual measured fan speed is compared against the target fan speed. These registers
are only used when the FSC is active.
This circuitry is used to indicate that the target fan speed at full drive is higher than the fan is actually
capable of reaching. If the measured fan speed does not exceed the target fan speed minus the Fan
Drive Fail Band Register settings for a period of time longer than set by the DRIVE_FAIL_CNTx[1:0]
bits, then the DRIVE_FAIL status bit will be set and an interrupt generated.
5.17
TACH Target Registers
The TACH Target Registers hold the target tachometer value that is maintained by the RPM-based
Fan Speed Control Algorithm.
The value in the TACH Target Registers will always reflect the current TACH Target value.
If one of the algorithms is enabled, setting the TACH Target Register to FFh will disable the fan driver
(set the fan drive setting to 0%). Setting the TACH Target to any other value (from a setting of FFh)
will cause the algorithm to invoke the Spin Up Routine after which it will function normally.
Table 5.26 Fan Drive Fail Band Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
3Ah
R/W
Fan 1 Drive
Fail Band
Low Byte
16
8
4
2
1
-
-
-
00h
3Bh
R/W
Fan 1 Drive
Fail Band
High Byte
4096
2048
1024
512
256
128
64
32
00h
4Ah
R/W
Fan 2 Drive
Fail Band
Low Byte
16
8
4
2
1
-
-
-
00h
4Bh
R/W
Fan 2 Drive
Fall Band
High Byte
4096
2048
1024
512
256
128
64
32
00h
Table 5.27 TACH Target Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
3Ch
R/W
TACH Target
1 Low Byte
16
84
21
-
-
-
F8h
3Dh
R/W
TACH Target
1 High Byte
4096
2048
1024
512
256
128
64
32
FFh
4Ch
R
TACH Target
2 Low Byte
16
84
21
-
-
-
F8h
4Dh
R/W
TACH Target
2 High Byte
4096
2048
1024
512
256
128
64
32
FFh



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