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EMC2302 Fiches technique(PDF) 25 Page - SMSC Corporation |
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EMC2302 Fiches technique(HTML) 25 Page - SMSC Corporation |
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25 / 44 page ![]() Dual RPM-Based PWM Fan Controller Datasheet SMSC EMC2302 25 Revision 1.1 (10-12-09) DATASHEET During Power-On-Reset (POR), the default values are stored in the registers. A POR is initiated when power is first applied to the part and the voltage on the VDD supply surpasses the POR level as specified in the electrical characteristics. Any reads to undefined registers will return 00h. Writes to undefined registers will not have an effect. 5.1.1 Lock Entries The Lock Column describes the locking mechanism, if any, used for individual registers. All SWL registers are Software Locked and therefore made read-only when the LOCK bit is set. 5.2 Configuration Register The Configuration Register controls the basic functionality of the EMC2302. The bits are described below. The Configuration Register is software locked. Bit 7 - MASK - Blocks the ALERT# pin from being asserted. 49h R/W Fan 2 Valid TACH Count Holds the tachometer reading that indicates Fan 2 is spinning properly F5h SWL Page 36 4Ah R/W Fan 2 Drive Fail Band Low Byte Stores the number of Tach counts used to determine how the actual fan speed must match the target fan speed at full scale drive 00h SWL Page 37 4Bh R/W Fan 2 Drive Fail Band High Byte 00h SWL 4Ch R/W TACH 2 Target Low Byte Holds the target tachometer setting low byte for Fan 2 F8h No Page 37 4Dh R/W TACH 2 Target High Byte Holds the target tachometer setting high byte for Fan 2 FFh No Page 37 4Eh R TACH 2 Reading High Byte Holds the tachometer reading high byte for Fan 2 FFh No Page 38 4Fh R TACH 2 Reading Low Byte Holds the tachometer reading low byte for Fan 2 F8h No Page 38 Lock Register EF R/W Software Lock Locks all SWL registers 00h SWL Page 39 Revision Registers FDh R Product ID Stores the unique Product ID 36h No Page 39 FEh R Manufacturer ID Stores the Manufacturer ID 5Dh No Page 39 FFh R Revision Revision 80h No Page 39 Table 5.2 Configuration Register ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 20h R/W Configuration MASK DIS_TO WD_EN - - - DR_EXT_ CLK USE_ EXT_ CLK 40h Table 5.1 EMC2302 Register Set (continued) ADDR R/W REGISTER NAME FUNCTION DEFAULT VALUE LOCK PAGE |
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