EMC2302 datasheet(26/44 Pages) SMSC

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Dual RPM-Based PWM Fan Controller

Datasheet

Revision 1.1 (10-12-09)

SMSC EMC2302

DATASHEET

‘0’ (default) - The ALERT# pin is unmasked. If any bit in either status register is set, the ALERT#

pins will be asserted (unless individually masked via the Mask Register).

‘1’ - The ALERT# pin is masked and will not be asserted.

Bit 6 - DIS_TO - Disables the SMBus timeout function for the SMBus client (if enabled).

‘0’ - The SMBus timeout function is enabled.

‘1’ (default) - The SMBus timeout function is disabled allowing the device to be fully I2C compliant.

Bit 5 - WD_EN - Enables the Watchdog timer to operate in Continuous Mode (see Section 4.8.2).

‘0’ (default) - The Watchdog timer does not operate continuously. It will function upon power up and

at no other time.

‘1’ - The Watchdog timer operates continuously as described in Section 4.8.

Bit 1 - DR_EXT_CLK - Enables the internal tachometer clock to be driven out on the CLK pin so that

multiple devices can be synced to the same source.

‘0’ (default) - The CLK pin acts as a clock input.

‘1’ - The CLK pin acts as a clock output and is a push-pull driver.

Bit 0 - USE_EXT_CLK - Enables the EMC2302 to use a clock present on the CLK pin as the

tachometer clock. If the DR_EXT_CLK bit is set, then this bit is ignored and the device will use the

internal oscillator.

‘0’ (default) - The EMC2302 will use its internal oscillator for all Tachometer measurements.

‘1’ - The EMC2302 will use the oscillator presented on the CLK pin for all Tachometer

measurements.

5.3

Fan Status Registers

The Fan Status registers contain the status bits associated with each fan driver.

5.3.1

Fan Status - 24h

The Fan Status register indicates that one or both of the fan drivers has stalled or failed or that the

Watchdog Timer has expired (see Section 4.8).

Bit 7 - WATCH - Indicates that the Watchdog Timer has expired. When set, each fan is driven to 100%

duty cycle and will remain at 100% duty cycle until they are programmed. This bit is cleared when it

is read.

Table 5.3 Fan Status Registers

ADDR

R/W

DEFAULT

24h

R-C

Fan Status

WATCH

DRIVE_

FAIL

FAN_

SPIN

FAN_

STALL

00h

25h

R-C

Fan Stall

Status

FAN2_

STALL

FAN1_

STALL

00h

26h

R-C

Fan Spin

Status

FAN2_

SPIN

FAN1_

SPIN

00h

27h

R-C

Fan Drive

Fail Status

DRIVE_

FAIL2

DRIVE_

FAIL1

00h

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