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EMC2302 Fiches technique(PDF) 36 Page - SMSC Corporation

No de pièce EMC2302
Description  Dual RPM-Based PWM Fan Controller
PDF  44 Pages
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Fabricant  SMSC [SMSC Corporation]
Site Internet  http://www.smsc.com
Logo SMSC - SMSC Corporation

EMC2302 Fiches technique(HTML) 36 Page - SMSC Corporation

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Dual RPM-Based PWM Fan Controller
Datasheet
Revision 1.1 (10-12-09)
36
SMSC EMC2302
DATASHEET
5.14
Fan Minimum Drive Registers
The Fan Minimum Drive registers store the minimum drive setting for each RPM-based Fan Speed
Control Algorithm. The RPM-based Fan Speed Control Algorithm will not drive the fan at a level lower
than the minimum drive unless the target Fan Speed is set at FFh (see Section 5.17).
During normal operation, if the fan stops for any reason (including low drive), the RPM-based Fan
Speed Control Algorithm will attempt to restart the fan. Setting the Fan Minimum Drive Register to a
setting that will maintain fan operation is a useful way to avoid potential fan oscillations as the control
circuitry attempts to drive it at a level that cannot support fan operation.
The Fan Minimum Drive Registers are software locked.
5.15
Valid TACH Count Registers
The Valid TACH Count registers store the maximum TACH Reading Register value to indicate that
each fan is spinning properly. The value is referenced at the end of the Spin Up Routine to determine
if the fan has started operating and decide if the device needs to retry. See Equation [2] in Section 5.18
for translating the count to an RPM.
If the TACH Reading Register value exceeds the Valid TACH Count Register (indicating that the Fan
RPM is below the threshold set by this count), then a stalled fan is detected. In this condition, the
algorithm will automatically begin its Spin Up Routine.
If a TACH Target setting is set above the Valid TACH Count setting, then that setting will be ignored
and the algorithm will use the current fan drive setting.
The Valid TACH Count registers are software locked.
Table 5.24 Minimum Fan Drive Registers
ADDR
R/W
REGISTER
B7B6B5
B4
B3
B2B1B0
DEFAULT
38h
R/W
Fan 1
Minimum
Drive
128
643216
8
4
2
1
66h
(40%)
48h
R/W
Fan 2
Minimum
Drive
128
643216
8
4
2
1
66h
(40%)
Table 5.25 Valid TACH Count Registers
ADDR
R/W
REGISTER
B7B6
B5
B4B3B2
B1B0
DEFAULT
39h
R/W
Valid TACH
Count 1
4096
2048
1024
512
256
128
64
32
F5h
49h
R/W
Valid TACH
Count 2
4096
2048
1024
512
256
128
64
32
F5h



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