EMC2302 datasheet(27/44 Pages) SMSC

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Dual RPM-Based PWM Fan Controller

Datasheet

SMSC EMC2302

Revision 1.1 (10-12-09)

DATASHEET

Bit 2 - DRIVE_FAIL - Indicates that one or both fan drivers cannot meet the programmed fan speed

at maximum PWM duty cycle. This bit is set when any bit in the Fan Drive Fail Status register is set

and cleared when all bits in the Fan Drive Fail Status register are cleared.

Bit 1 - FAN_SPIN - Indicates that one or both fan drivers cannot spin up. This bit is set when any bit

in the Fan Spin Status register is set and cleared when all of the bits in the Fan Spin Status register

are cleared.

Bit 0 - FAN_STALL - Indicates that one or both fan drivers have stalled. This bit is set when any bit in

the Fan Stall Status register is set and cleared when all of the bits in the Fan Stall Status register are

cleared.

5.3.2

Fan Stall Status - 25h

The Fan Stall Status register indicates which fan driver has detected a stalled condition (see

Section 4.4.1). All bits are cleared upon a read if the error condition has been removed.

Bit 1 - FAN2_STALL - Indicates that Fan 2 has stalled.

Bit 0 - FAN1_STALL - Indicates that Fan 1 has stalled.

5.3.3

Fan Spin Status - 26h

The Fan Spin Status register indicates which fan driver has failed to spin-up (see Section 4.6). All bits

are cleared upon a read if the error condition has been removed.

Bit 1 - FAN2_SPIN - Indicates that Fan 2 has failed to spin up.

Bit 0 - FAN_SPIN - Indicates that Fan 1 has failed to spin up.

5.3.4

Fan Drive Fail Status - 27h

The Fan Drive Fail Status register indicates which fan driver cannot drive to the programmed speed

even at 100% duty cycle (see Section 4.4.2 and Section 5.12). All bits are cleared upon a read if the

error condition has been removed.

Bit 1 - DRIVE_FAIL2 - Indicates that Fan 2 cannot reach its programmed fan speed even at 100% duty

cycle. This may be due to an aging fan or invalid programming.

Bit 0 - DRIVE_FAIL1 - Indicates that Fan 1 cannot reach its programmed fan speed even at 100% duty

cycle. This may be due to an aging fan or invalid programming.

5.4

Fan Interrupt Enable Register

The Fan Interrupt Enable controls the masking for each Fan channel. When a channel is enabled, it

will cause the ALERT# pin to be asserted when an error condition is detected.

Bit 1 - FAN2_INT_EN - Allows Fan 2 to assert the ALERT# pin if an error is detected.

Bit 0 - FAN1_INT_EN - Allows Fan 1 to assert the ALERT# pin if an error condition is detected.

Table 5.4 Fan Interrupt Enable Register

ADDR

R/W

B7B6B5B4

B1B0

DEFAULT

29h

R/W

Fan

Interrupt

Enable

----

FAN2_

INT_EN

FAN1_

INT_EN

00h

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