EMC2302 datasheet(12/44 Pages) SMSC

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Dual RPM-Based PWM Fan Controller

Datasheet

Revision 1.1 (10-12-09)

SMSC EMC2302

DATASHEET

Chapter 3 Communications

3.1

System Management Bus Interface Protocol

The EMC2302 communicates with a host controller, such as an SMSC SIO, through the SMBus. The

SMBus is a two-wire serial communication protocol between a computer host and its peripheral

devices. A detailed timing diagram is shown in Figure 3.1. Stretching of the SMCLK signal is supported;

however, the EMC2302 will not stretch the clock signal.

3.1.1

SMBus Start Bit

The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic

‘0’ state while the SMBus Clock line is in a logic ‘1’ state.

3.1.2

SMBus Address and RD / WR Bit

The SMBus Address Byte consists of the 7-bit client address followed by a RD / WR indicator bit. If

this RD / WR bit is a logic ‘0’, then the SMBus Host is writing data to the client device. If this RD / WR

bit is a logic ‘1’, then the SMBus Host is reading data from the client device.

The EMC2103-1 SMBus address is set at 0101_110(r/w)b.

The EMC2103-2 SMBus address is set at 0101_111(r/w)b.

3.1.3

SMBus Data Bytes

All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.

3.1.4

SMBus ACK and NACK Bits

The SMBus client will acknowledge all data bytes that it receives (as well as the client address if it

matches and the ARA address if the ALERT# pin is asserted). This is done by the client device pulling

the SMBus Data line low after the 8th bit of each byte that is transmitted.

The Host will NACK (not acknowledge) the data received from the client by holding the SMBus data

line high after the 8th data bit has been sent.

Figure 3.1 SMBus Timing Diagram

SMDATA

SMCLK

TLOW

TRISE

THIGH

TFALL

TBUF

THD:STA

S - Start Condition

P - Stop Condition

THD:DAT

TSU:DAT

TSU:STA

THD:STA

TSU:STO

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